CMOS-COMPATIBLE POLYCIDE FUSE STRUCTURE AND METHOD OF FABRICATING SAME

• US 20160056162A1
• Filed: 06/25/2013
• Published: 02/25/2016
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Chia-Hong Jan, Jeng-Ya D. Yeh, Joodong Park, Walid M. Hafez
• Inventors: YEH, JENG-YA D., JAN, CHIA-HONG, HAFEZ, WALID M., PARK, JOODONG
• Granted Patent: US 9,881,927 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

CMOS-compatible polycide fuse structures and methods of fabricating CMOS-compatible polycide fuse structures are described. In an example, a semiconductor structure includes a substrate. A polycide fuse structure is disposed above the substrate and includes silicon and a metal. A metal oxide semiconductor (MOS) transistor structure is disposed above the substrate and includes a metal gate electrode.

Claims

1. A semiconductor structure, comprising:

a substrate;

a polycide fuse structure disposed above the substrate and comprising silicon and a metal; and

a metal oxide semiconductor (MOS) transistor structure disposed above the substrate, the MOS transistor structure comprising a metal gate electrode.

2. The semiconductor structure of claim 1, wherein the polycide fuse structure is not programmed and comprises a layer of metal silicide on a layer of polysilicon.

3. The semiconductor structure of claim 1, wherein the polycide fuse structure is programmed and comprises a mixture of the silicon and the metal.

4. The semiconductor structure of claim 1, wherein the MOS transistor structure further comprises a high-k gate dielectric layer.

5. The semiconductor structure of claim 4, wherein the high-k gate dielectric layer is disposed between the metal gate electrode and the substrate, and along sidewalls of the metal gate electrode.

6. The semiconductor structure of claim 1, wherein the metal of the polycide fuse structure is nickel or cobalt.

7. The semiconductor structure of claim 1, wherein the substrate is a bulk single crystalline silicon substrate, the MOS transistor structure is disposed on the bulk single crystalline silicon substrate, and the polycide fuse structure is disposed on an isolation region disposed in the bulk single crystalline silicon substrate.

8. A semiconductor structure, comprising:

first and second semiconductor fins disposed above a substrate;

a polycide fuse structure disposed above the first semiconductor fin but not above the second semiconductor fin, the polycide fuse structure comprising silicon and a metal; and

a metal oxide semiconductor (MOS) transistor structure formed from the second semiconductor fin but not from the first semiconductor fin, the MOS transistor structure comprising a metal gate electrode.

9. The semiconductor structure of claim 8, wherein the polycide fuse structure is not programmed and comprises a layer of metal silicide on a layer of polysilicon.

10. The semiconductor structure of claim 8, wherein the polycide fuse structure is programmed and comprises a mixture of the silicon and the metal.

11. The semiconductor structure of claim 8, wherein the MOS transistor structure further comprises a high-k gate dielectric layer.

12. The semiconductor structure of claim 11, wherein the high-k gate dielectric layer is disposed between the metal gate electrode and the second semiconductor fin, and along sidewalls of the metal gate electrode.

13. The semiconductor structure of claim 8, wherein the metal of the polycide fuse structure is nickel or cobalt.

14. The semiconductor structure of claim 8, wherein the polycide fuse structure is disposed on an electrically insulating layer disposed on the first semiconductor fin.

15. The semiconductor structure of claim 8, wherein the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins, wherein the polycide fuse structure is disposed above the first plurality of semiconductor fins but not above the second plurality of semiconductor fins, and wherein the MOS transistor structure is formed from the second plurality of semiconductor fins but not from the first plurality of semiconductor fins.

16. The semiconductor structure of claim 15, wherein the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.

17. The semiconductor structure of claim 8, wherein the polycide fuse structure is a non-planar polycide fuse structure.

18. A semiconductor structure, comprising:

first and second semiconductor fins disposed above a substrate;

an isolation region disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins;

a polycide fuse structure disposed above the isolation region but not above the first and second semiconductor fins, the polycide fuse structure comprising silicon and a metal; and

first and second metal oxide semiconductor (MOS) transistor structures formed from the first and second semiconductor fins, respectively, the MOS transistor structures each comprising a metal gate electrode.

19. The semiconductor structure of claim 18, wherein the polycide fuse structure is not programmed and comprises a layer of metal silicide on a layer of polysilicon.

20. The semiconductor structure of claim 18, wherein the polycide fuse structure is programmed and comprises a mixture of the silicon and the metal.

21. The semiconductor structure of claim 18, wherein each of the first and second the MOS transistor structures further comprises a high-k gate dielectric layer, and wherein the high-k gate dielectric layer is disposed between the metal gate electrode and the respective first or second semiconductor fin, and along sidewalls of the metal gate electrode.

22. The semiconductor structure of claim 18, wherein the metal of the polycide fuse structure is nickel or cobalt.

23. The semiconductor structure of claim 18, wherein the first semiconductor fin is of a first plurality of semiconductor fins and the second semiconductor fin is of a second plurality of semiconductor fins, wherein the first MOS transistor structure is formed from the first plurality of semiconductor fins and the second MOS transistor structure is formed from the second plurality of semiconductor fins, and wherein the first and second pluralities of semiconductor fins are electrically coupled to an underlying bulk semiconductor substrate.

24. The semiconductor structure of claim 18, wherein the polycide fuse structure is a planar polycide fuse structure.

25. The semiconductor structure of claim 18, wherein the polycide fuse structure has an uppermost surface at a height less than the heights of the first and second semiconductor fins.