METHODS OF FORMING FIELD EFFECT TRANSISTORS USING A GATE CUT PROCESS FOLLOWING FINAL GATE FORMATION

• US 20160056181A1
• Filed: 08/19/2014
• Published: 02/25/2016
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent A., Nowak, Edward J.
• Granted Patent: US 9,373,641 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 : adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 : with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6681 : using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability

Abstract

Disclosed are field effect transistor (FET) formation methods using a final gate cut process and the resulting structures. One method forms an elongated gate across first and second semiconductor bodies for first and second FETs, respectively. An opening is formed in a portion of the elongated gate between the semiconductor bodies, cutting at least the gate conductor layer. The opening is filled with an isolation layer, thereby forming an isolation region that segments the elongated gate into first and second gates for the first and second FETs, respectively. Another method forms at least three gates across an elongated semiconductor body. An isolation region is formed that extends, not only through a portion of a center one of the gates, but also through a corresponding portion of the elongated semiconductor body adjacent to that gate, thereby segmenting the elongated semiconductor body into discrete semiconductor bodies for first and second FETs.

Claims

1. A method of forming a semiconductor structure, said method comprising:

forming multiple semiconductor bodies comprising at least a first semiconductor body for a first field effect transistor and a second semiconductor body for a second field effect transistor parallel to said first semiconductor body;

forming an elongated gate that traverses said multiple semiconductor bodies and that is laterally surrounded by a gate sidewall spacer, said elongated gate comprising a gate conductor layer; and

,

after said forming of said elongated gate, forming an isolation region in a portion of said elongated gate between said first semiconductor body and said second semiconductor body, said isolation region comprising;

an opening that extends vertically into said portion of said elongated gate and that cuts at least said gate conductor layer into discrete segments; and

,

an isolation layer within said opening positioned laterally between and immediately adjacent to said discrete segments,

said isolation region segmenting said elongated gate into a first gate for said first field effect transistor and a second gate for said second field effect transistor and electrically isolating said first gate from said second gate.

2. The method of claim 1, said forming of said multiple semiconductor bodies comprising forming said multiple semiconductor bodies on any one of a bulk semiconductor wafer and a semiconductor-on-insulator wafer.

3. The method of claim 1, said forming of said multiple semiconductor bodies comprising forming multiple semiconductor fins and said forming of said elongated gate comprising forming said elongated gate adjacent to opposing sides and tops of said multiple semiconductor fins.

4. The method of claim 1, said opening having a width that is less than a distance between said first semiconductor body and said second semiconductor body and a length that entirely traverses said elongated gate and further extends laterally into and through opposing sections of said gate sidewall spacer adjacent to said portion of said elongated gate.

5. The method of claim 1, said opening having a width that is less than a distance between said first semiconductor body and said second semiconductor body and a length that traverses said gate conductor layer without further extending laterally into opposing sections of said gate sidewall spacer adjacent to said portion of said elongated gate.

6. The method of claim 1, further comprising:

after said forming of said multiple semiconductor bodies and before said forming of said elongated gate, forming a dummy gate that traverses channel regions of said multiple semiconductor bodies;

forming said gate sidewall spacer adjacent to vertical sidewalls of said dummy gate so that said gate sidewall spacer laterally surrounds said dummy gate;

after said forming of said dummy gate and said gate sidewall spacer, performing at least one dopant implantation process so as to at least dope source/drain regions in exposed portions of said multiple semiconductor bodies;

forming a dielectric layer over said dummy gate, said gate sidewall spacer and said exposed portions of said multiple semiconductor bodies;

planarizing said dielectric layer so as to expose a top surface of said dummy gate; and

,

selectively removing said dummy gate to form a trench and replacing said dummy gate with said elongated gate in said trench such that said elongated gate is laterally surrounded by said gate sidewall spacer.

7. The method of claim 6, said forming of said elongated gate in said trench comprising forming a replacement metal gate by:

forming a conformal high-K gate dielectric layer within said trench; and

forming said gate conductor layer on said conformal high-K gate dielectric layer such that said conformal high-K gate dielectric layer is positioned between said gate conductor layer and said multiple semiconductor bodies and further positioned between said gate conductor layer and said gate sidewall spacer,

said gate conductor layer being formed so as to comprise at least one metal.

8. A semiconductor structure comprising:

multiple semiconductor bodies comprising at least a first semiconductor body for a first field effect transistor and a second semiconductor body for a second field effect transistor parallel to said first semiconductor body;

an elongated gate traversing said multiple semiconductor bodies and comprising a gate conductor layer;

a gate sidewall spacer laterally surrounding said elongated gate; and

,

an isolation region in a portion of said elongated gate between said first semiconductor body and said second semiconductor body, said isolation region comprising;

an opening that extends vertically into said portion of said elongated gate and that cuts at least said gate conductor layer into discrete segments; and

,

an isolation layer within said opening positioned laterally between and immediately adjacent to said discrete segments,

said isolation region segmenting said elongated gate into a first gate for said first field effect transistor and a second gate for said second field effect transistor and electrically isolating said first gate from said second gate.

9. The semiconductor structure of claim 8, said multiple semiconductor bodies being on any one of a bulk semiconductor substrate and an insulator layer.

10. The semiconductor structure of claim 8, said multiple semiconductor bodies comprising multiple semiconductor fins and said elongated gate being adjacent to opposing sides and tops of said semiconductor fins.

11. The semiconductor structure of claim 8, said isolation region being parallel to said first semiconductor body and said second semiconductor body, completely traversing said portion of said elongated gate, extending laterally into and through opposing sections of said gate sidewall spacer adjacent to said portion of said elongated gate, and further extending vertically through a gate dielectric layer within said portion of said elongated gate.

12. The semiconductor structure of claim 8, said isolation region being parallel to said first semiconductor body and said second semiconductor body, being between opposing sections of said gate sidewall spacer, and further extending vertically through said portion of said elongated gate to a gate dielectric layer within said portion of said elongated gate.

13. The semiconductor structure of claim 8, said elongated gate comprising a replacement metal gate comprising a conformal high-K gate dielectric layer positioned between said gate conductor layer and said multiple semiconductor bodies and further positioned between said gate conductor layer and said gate sidewall spacer, said gate conductor layer comprising at least one metal.

14. A method of forming a semiconductor structure, said method comprising:

forming an elongated semiconductor body;

forming multiple gates across said elongated semiconductor body, said multiple gates comprising a first gate for a first field effect transistor, a second gate for a second field effect transistor and a third gate between said first gate and said second gate;

after said forming of said multiple gates, forming an isolation region that extends through a portion of said third gate and further through a corresponding portion of said elongated semiconductor body adjacent to said third gate, said isolation region segmenting said elongated semiconductor body into a first semiconductor body for said first field effect transistor and a second semiconductor body for said second field effect transistor and electrically isolating said first semiconductor body from said second semiconductor body; and

,

forming contacts to said first gate and said second gate.

15. The method of claim 14, said forming of said isolation region comprising:

forming an opening that extends through said portion of said third gate and further through said corresponding portion of said elongated semiconductor body in order to physically segment said elongated semiconductor body into said first semiconductor body and said second semiconductor body; and

,

forming at least one isolation layer within said opening.

16. The method of claim 14, said forming of said isolation region comprising:

forming an opening that extends through said portion of said third gate and exposes said corresponding portion of said elongated semiconductor body;

performing a dopant implantation process to form a dopant implant region in said corresponding portion of said elongated semiconductor body; and

,

forming at least one isolation layer within said opening.

17. The method of claim 14, said forming of said elongated semiconductor body comprising forming said elongated semiconductor body on any one of a bulk semiconductor wafer and a semiconductor-on-insulator wafer.

18. The method of claim 14, said forming of said elongated semiconductor body comprising forming an elongated semiconductor fin and said forming of said multiple gates comprising forming said multiple gates adjacent to opposing sides and a top of said elongated semiconductor fin.

19. The method of claim 14, said forming of said multiple gates comprising forming replacement metal gates, each replacement metal gate being laterally surrounded by a gate sidewall spacer and comprising a conformal high-K gate dielectric layer and a gate conductor layer on said conformal high-K gate dielectric layer such that said conformal high-K gate dielectric layer is positioned between said gate conductor layer and said elongated semiconductor body and further positioned between said gate conductor layer and said gate sidewall spacer, said gate conductor layer comprising at least one metal.

20. A semiconductor structure comprising:

an elongated semiconductor body;

multiple gates across said elongated semiconductor body, said multiple gates comprising a first gate for a first field effect transistor, a second gate for a second field effect transistor and a third gate between said first gate and said second gate;

an isolation region that extends through a portion of said third gate and further through a corresponding portion of said elongated semiconductor body adjacent to said third gate, said isolation region segmenting said elongated semiconductor body into a first semiconductor body for said first field effect transistor and a second semiconductor body for said second field effect transistor and electrically isolating said first semiconductor body from said second semiconductor body; and

,

contacts to said first gate and said second gate.

21. The semiconductor structure of claim 20, said isolation region comprising:

an opening that extends through said portion of said third gate and further through said corresponding portion of said elongated semiconductor body in order to physically segment said elongated semiconductor body into said first semiconductor body and said second semiconductor body; and

,

at least one isolation layer within said opening.

22. The semiconductor structure of claim 20, said isolation region comprising:

an opening that extends through said portion of said third gate;

a dopant implant region in said corresponding portion of said elongated semiconductor body exposed within said opening; and

,

at least one isolation layer within said opening.

23. The semiconductor structure of claim 20, said elongated semiconductor body being on any one of a bulk semiconductor substrate and an insulator layer.

24. The semiconductor structure of claim 20, said elongated semiconductor body comprising an elongated semiconductor fin and said multiple gates being adjacent to opposing sides and a top of said elongated semiconductor fin.

25. The semiconductor structure of claim 20, said multiple gates comprising replacement metal gates, each replacement metal gate being laterally surrounded by a gate sidewall spacer and comprising a conformal high-K gate dielectric layer and a gate conductor layer on said conformal high-K gate dielectric layer such that said conformal high-K gate dielectric layer is positioned between said gate conductor layer and said elongated semiconductor body and further positioned between said gate conductor layer and said gate sidewall spacer, said gate conductor layer comprising at least one metal.