CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME

• US 20160056208A1
• Filed: 08/25/2014
• Published: 02/25/2016
• Est. Priority Date: 08/25/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pellizzer, Fabio, Tortorelli, Innocenzo, Ghetti, Andrea
• Granted Patent: US 9,768,378 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

Claims

1. A method of fabricating a memory array, comprising:

forming a plurality of line stacks, wherein each line stack includes a storage material line disposed over a lower conductive line;

forming a plurality of upper conductive lines on and crossing the line stacks, wherein forming the upper conductive lines exposes portions of the line stacks between adjacent upper conductive lines;

after forming the upper conductive lines, forming a plurality of storage elements at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from the storage material lines such that each storage element is laterally surrounded by spaces; and

forming a continuous sealing material laterally surrounding each of the storage elements.

2. The method of claim 1, wherein:

forming the line stacks comprises using a first photo mask to pattern a material stack including a storage material disposed over a lower conductive material;

forming the upper conductive lines comprises using a second photo mask to pattern an upper conductive material; and

forming the storage elements comprises etching without using an additional photo mask.

3. The method of claim 1, further comprising:

after forming the plurality of line stacks, filling gaps between the line stacks with an initial isolation material; and

after forming the plurality of upper conductive lines and before forming the storage elements, removing at least an upper portion of the initial isolation material to expose sidewalls of the storage material lines.

4. The method of claim 3, wherein forming the plurality of line stacks further includes forming a plurality of selector material lines interposed between the storage material lines and the lower conductive lines.

5. The method of claim 4,

wherein removing the at least an upper portion of the initial isolation material includes further removing lower portions of the initial isolation material to expose sidewalls of the selector material lines,

further comprising after forming the upper conductive lines, forming a plurality of selector elements interposed between storage elements and the lower conductive lines by removing selector materials from the selector material lines such that each selector element is laterally surrounded by the spaces, and

wherein forming the continuous sealing material further comprises laterally surrounding each of the selector elements.

6. The method of claim 4, wherein removing the at least an upper portion of the initial isolation material includes leaving lower portions of the initial isolation material such that sidewalls of the selector material lines remain unexposed.

7. The method of claim 1, further comprising, after forming the sealing material, further surrounding the storage elements with an isolation material by filling the spaces laterally around the storage elements.

8. The method of claim 1, wherein forming the line stacks comprises forming and patterning storage materials including phase change materials.

9. The method of claim 1, further comprising, after forming the line stacks, forming initial sealing materials on sidewalls of the line stacks prior to forming the storage elements.

10. The method of claim 9,

wherein forming the storage elements includes removing the initial sealing materials on sidewalls of the storage material line of the exposed portions of the line stacks, and

wherein forming the continuous sealing material comprises forming the sealing material on remaining initial sealing materials on first opposing sidewalls of the each of the storage element, and forming the sealing material on second opposing sidewalls of the each of the storage elements.

11. The method of claim 1, wherein forming the line stacks further comprises forming the each line stack including a selector material line interposed between the lower conductive line and the storage material line.

12. The method of claim 11, further comprising, after forming the upper conductive lines, forming a plurality of selector elements, wherein each storage element is vertically interposed between one of the storage elements and a lower conductive line.

13. The method of claim 12, wherein forming the continuous sealing material further comprises laterally surrounding each of the selector elements.

14. A method of fabricating a memory device, comprising:

forming a line stack comprising a memory cell line stack disposed on a lower conductive line;

forming an upper conductive line intersecting the line stack to form an overlapping region between the line stack and the upper conductive line;

forming a free-standing pillar at the overlapping region by removing at least an upper portion of the memory cell line stack from non-overlapping regions adjacent the overlapping region; and

forming a continuous sealing material covering lateral surfaces of the free standing pillar.

15. The method of claim 14, wherein forming the line stack is performed using a first photolithography mask, forming the upper conductive line is performed using a second photolithography mask, and forming the free-standing pillar is performed without an additional photolithography process.

16. The method of claim 14,

wherein forming the line stack includes forming a lower active element line of the memory cell stack over the lower conductive line and an upper active element line over the lower active element line, and

wherein one of the upper and lower active element lines comprises a storage element line and the other of the upper and lower active materials comprises a selector element line.

17. The method of claim 16, wherein forming the free-standing pillar includes removing the upper active element line from the non-overlapping regions of the cell line stack to form an upper active element.

18. The method of claim 17, wherein the upper active element comprises the storage element.

19. The method of claim 16, wherein forming the free-standing pillar further includes removing the lower active element line from the non-overlapping regions of the cell line stack to form a lower active element.

20. The method of claim 19, wherein forming the free-standing pillar includes forming the lower active element after forming the continuous sealing material.

21. A method of fabricating a memory array, comprising:

forming a plurality of line stacks and initial isolation dielectric materials, wherein the line stacks and the initial isolation dielectric materials alternate in a lateral direction;

forming a plurality of upper conductive lines on the alternating memory cell line stacks and the initial isolation dielectric materials, the upper conductive lines crossing the line stacks, wherein forming the upper conductive lines exposes portions of the alternating line stacks and the initial isolation dielectric materials between adjacent upper conductive lines;

removing upper portions of the initial isolation dielectric materials;

removing upper portions of exposed portions of the line stacks to form free-standing pillars at intersections of the lower conductive lines and the upper conductive lines; and

after removing the upper portions of the initial isolation dielectric materials, lining to surround upper portions of the free-standing pillars with a continuous liner material.

22. The method of claim 21, wherein each of the line stacks includes a lower conductive line, a lower active element line over the lower conductive line and an upper active element line over the lower active element line, and

wherein forming the free-standing pillars includes forming upper active elements surrounded by spaces.

23. The method of claim 22, further comprising:

removing lower portions of the initial isolation dielectric materials; and

removing lower portions of exposed portions of the line stacks to form the free-standing pillars,

wherein forming the free-standing pillars further includes removing lower portions of the line stacks to form lower active elements surrounded by spaces.

24. The method of claim 23, wherein the upper active elements are storage elements and the lower active elements are selector elements.

25. The method of claim 22, further comprising:

after lining, removing lower portions of the line stacks to form lower active elements.

26. A memory device, comprising

a plurality of lower conductive lines extending in a first direction;

a plurality of upper conductive lines extending in a second direction crossing the first direction;

a plurality of memory cell pillars formed at intersections between the lower conductive lines and the upper conductive lines, wherein each of the memory pillars comprise a storage material element laterally surrounded by a continuous sealing material, wherein the continuous sealing material extends to line opposing sidewalls of the upper conductive line connected to the each of the memory pillars.

27. The memory device of claim 26, wherein the storage element of the each of the memory pillars comprises a chalcogenide material configured to switch between crystalline and amorphous phases during an access operation via an electrical pulse applied between one of the lower conductive lines and one of the upper conductive lines.

28. The memory device of claim 27, wherein the sealing material laterally encloses the storage element in both first and second directions such that during an access operation to access a target storage element, the temperature of an adjacent neighboring storage element in the first direction is substantially the same as the temperature of an adjacent neighboring storage element in the second direction.

29. The memory array of claim 28, wherein the sealing material further encloses an initial sealing material formed on opposing first sidewalls of each of the storage elements, the first sidewalls extending in the first direction.

30. The memory array of claim 28, wherein the sealing material contacts opposing second sidewalls of each of the storage elements, the second sidewalls extending in the second direction.

31. A memory device, comprising

a lower conductive line extending in a first lateral direction;

an upper conductive line extending in a second lateral direction crossing the first lateral direction;

a memory cell stack formed at an intersection between the lower and upper conductive lines, the memory cell stack comprising;

a first active element disposed over the lower conductive line,

a second active element disposed over the first active element,

wherein one of the first and second active elements comprises a storage material and the other of the first and second active materials comprises a selector material; and

a continuous sealing material laterally surrounding the second active element and extending to cover sidewalls of the upper conductive line.

32. The memory device of claim 31 further comprising an isolation material continuously surrounding the continuous sealing material, wherein the isolation material comprises a dielectric material different from the continuous sealing material.

33. The memory device of claim 31, wherein the continuous sealing material comprises silicon nitride.

34. The memory device of claim 31, wherein the continuous sealing material further laterally surrounds the first active element.

35. The memory device of claim 31, wherein the second active element comprises the storage element and the first active element comprises the selector element, wherein the storage element comprises a first chalcogenide material.

36. The memory device of claim 35, wherein the selector element comprises a second chalcogenide material different from the first chalcogenide material.

37. The memory device of claim 31, wherein the continuous sealing material contacts opposing sidewalls of second active element extending in the second direction.

38. The memory device of claim 37, further comprising an isolation material surrounding the continuous sealing material.