SILICON AND SILICON GERMANIUM NANOWIRE FORMATION

• US 20160056236A1
• Filed: 11/02/2015
• Published: 02/25/2016
• Est. Priority Date: 08/20/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Diaz, Carlos H., Colinge, Jean-Pierre
• Granted Patent: US 9,634,091 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

Claims

1. A semiconductor arrangement, comprising:

a first nanowire transistor formed on a substrate, the first nanowire transistor comprising;

a first germanium nanowire channel formed between a first source region and a first drain region, wherein a distance between a surface of the substrate underlying the first germanium nanowire channel and a bottom surface of the first germanium nanowire channel corresponds to a first distance; and

a second nanowire transistor formed on the substrate, the second nanowire transistor comprising;

a first silicon nanowire channel formed between a second source region and a second drain region, wherein a distance between a surface of the substrate underlying the first silicon nanowire channel and a bottom surface of the first silicon nanowire channel corresponds to a second distance different than the first distance.

2. The semiconductor arrangement of claim 1, wherein the second distance is less than the first distance.

3. The semiconductor arrangement of claim 1, wherein a diameter of the first silicon nanowire channel is different than a diameter of the first germanium nanowire channel.

4. The semiconductor arrangement of claim 1, wherein a diameter of the first silicon nanowire channel is between about 20% and about 40% larger than a diameter of the first germanium nanowire channel.

5. The semiconductor arrangement of claim 1, wherein the first nanowire transistor comprises:

a second germanium nanowire channel formed between the first source region and the first drain region, the second germanium nanowire channel overlying the first germanium nanowire channel.

6. The semiconductor arrangement of claim 5, wherein the first nanowire transistor comprises:

a first dielectric layer surrounding a circumference of the first germanium nanowire channel;

a second dielectric layer surrounding a circumference of the second germanium nanowire channel; and

a gate electrode formed around the first dielectric layer and the second dielectric layer, wherein a portion of the gate electrode is disposed between the first dielectric layer and the second dielectric layer.

7. The semiconductor arrangement of claim 5, wherein the first nanowire transistor comprises:

a first dielectric layer surrounding a circumference of the first germanium nanowire channel;

a second dielectric layer surrounding a circumference of the second germanium nanowire channel; and

a gate electrode formed around the first dielectric layer and the second dielectric layer, wherein a spacer between the first dielectric layer and the second dielectric layer is void of the gate electrode.

8. The semiconductor arrangement of claim 5, wherein the first nanowire transistor comprises:

an interfacial layer surrounding the first germanium nanowire channel and the second germanium nanowire channel, the interfacial layer pinching off a space between the first germanium nanowire channel and the second germanium nanowire channel.

9. The semiconductor arrangement of claim 8, comprising:

a dielectric layer surrounding the interfacial layer; and

a gate electrode surrounding the dielectric layer.

10. The semiconductor arrangement of claim 1, wherein the first nanowire transistor comprises:

a dielectric layer surrounding a circumference of the first germanium nanowire channel; and

a gate electrode formed around the dielectric layer.

11. The semiconductor arrangement of claim 10, wherein the gate electrode surrounds a circumference of the dielectric layer.

12. A semiconductor arrangement, comprising:

a first nanowire transistor comprising;

a first germanium nanowire channel formed between a first source region and a first drain region; and

a first gate structure formed around the first germanium nanowire channel; and

a second nanowire transistor comprising;

a first silicon nanowire channel formed between a second source region and a second drain region.

13. The semiconductor arrangement of claim 12, wherein the first nanowire transistor comprises:

a second germanium nanowire channel formed between the first source region and the first drain region, at least some of the first gate structure formed around the second germanium nanowire channel.

14. The semiconductor arrangement of claim 12, wherein the second nanowire transistor comprises:

a second gate structure formed around the first silicon nanowire channel.

15. The semiconductor arrangement of claim 12, wherein the second nanowire transistor comprises:

a second silicon nanowire channel formed between the second source region and the second drain region.

16. The semiconductor arrangement of claim 12, comprising:

an interfacial layer between the first germanium nanowire channel and the first gate structure.

17. The semiconductor arrangement of claim 12, comprising:

a high-k dielectric layer formed between the first germanium nanowire channel and the first gate structure.

18. The semiconductor arrangement of claim 12, wherein a diameter of the first silicon nanowire channel is different than a diameter of the first germanium nanowire channel.

19. A semiconductor arrangement, comprising:

a PMOS nanowire transistor comprising;

a first germanium nanowire channel formed between a first source region and a first drain region; and

a first gate structure formed around the first germanium nanowire channel; and

an NMOS nanowire transistor comprising;

a first silicon nanowire channel formed between a second source region and a second drain region; and

a second gate structure formed around the first silicon nanowire channel, wherein the first gate structure has a first gate height and the second gate structure has a second gate height different than the first gate height.

20. The semiconductor arrangement of claim 19, wherein the PMOS nanowire transistor comprises a second germanium nanowire channel and the NMOS nanowire transistor comprises a second silicon nanowire channel.