NANOSTRUCTURES AND NANOFEATURES WITH Si (111) PLANES ON Si (100) WAFERS FOR III-N EPITAXY

• US 20160056244A1
• Filed: 06/28/2013
• Published: 02/25/2016
• Est. Priority Date: 06/28/2013
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: DASGUPTA, Sansaptak, THEN, Han Wui, RADOSAVLJEVIC, Marko, CHAU, Robert S., GARDNER, Sanaz K., CHU-KUNG, Benjamin, SUNG, Seung Hoon
• Application Number:
  US14/779,257
• Publication Number:
  US 20160056244A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions

Abstract

A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation.

Claims

1. A method to manufacture an electronic device, comprising:

modifying a fin over an insulating layer on a substrate aligned along a first crystal orientation to form a surface aligned along a second crystal orientation; and

depositing a device layer over the surface of the fin aligned along the second crystal orientation.

2. The method of claim 1, further comprising

depositing a nucleation layer between the fin and the device layer.

3. The method of claim 1, wherein modifying the fin comprises

etching the fin to expose the surface aligned along the second crystal orientation.

4. The method of claim 1, wherein modifying the fin comprises

annealing the fin to form the surface aligned along the second crystal orientation.

5. The method of claim 1, wherein the substrate includes silicon, and the device layer includes a III-V material.

6. The method of claim 1, further comprising

depositing a polarization inducing layer on the device layer to provide a two-dimensional electron gas.

7. The method of claim 1, further comprising

etching the substrate through a mask to form the fin;

and

depositing the insulating layer on the substrate.

8. The method of claim 1, wherein the first crystal orientation is a <

100>

crystal orientation, and the second crystal orientation is a <

111>

crystal orientation.

9. The method of claim 1, wherein the thickness of the device layer is from 1 nanometer to 40 nanometers.

10. The method of claim 1, wherein the width of the first fin is less than the height of the first fin

11. An electronic device, comprising

a fin over an insulating layer on a substrate aligned along a first crystal orientation, the fin having a first surface aligned along a second crystal orientation;

and

a device layer deposited over the first surface of the fin aligned along the second crystal orientation.

12. The electronic device of claim 11, further comprising

a nucleation layer between the fin and the device layer.

13. The electronic device of claim 11, further comprising a polarization inducing layer on the device layer to provide a two-dimensional electron gas.

14. The electronic device of claim 11, wherein the fin has a second surface aligned along the second crystal orientation adjacent to the first surface.

15. The electronic device of claim 11, wherein the fin has a triangular shape.

16. The electronic device of claim 11, wherein the fin has a V shape.

17. The electronic device of claim 11, wherein the fin has an M shape.

18. The electronic device of claim 11, wherein the substrate includes silicon;

and the device layer includes a III-V material.

19. The electronic device of claim 11, wherein the first crystal orientation is a <

100>

crystal orientation, and the second crystal orientation is a <

111>

crystal orientation.

20. The electronic device of claim 11, wherein the thickness of the device layer is from 1 nanometer to 40 nanometers.