Recessed Salicide Structure to Integrate a Flash Memory Device with a High K, Metal Gate Logic Device

• US 20160056250A1
• Filed: 09/10/2014
• Published: 02/25/2016
• Est. Priority Date: 08/25/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Wei Cheng, Liu, Shih-Chang, Kao, Ya-Chen, Chuang, Harry Hak-Lay
• Granted Patent: US 9,735,245 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Some embodiments of the present disclosure provide an integrated circuit (IC) for an embedded flash memory device. The IC includes a flash memory cell having a memory cell gate. A silicide contact pad is arranged in a recess of the memory cell gate. A top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate. Dielectric side-wall spacers extend along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

Claims

1. An integrated circuit (IC) for an embedded flash memory device, the integrated circuit comprising:

a flash memory cell having a memory cell gate; and

a silicide contact pad arranged in a recess of the memory cell gate, wherein a top surface of the silicide contact pad is recessed relative to a top surface of the memory cell gate; and

dielectric sidewall spacers extending along sidewalls of the recess from the top surface of the memory cell gate to the top surface of the silicide contact pad.

2. The IC of claim 1, further comprising a vertical contact extending through the recess and coupled to the silicide contact pad.

3. The IC of claim 1, wherein the memory cell gate is a memory gate extending over a channel region of the flash memory cell.

4. The IC of claim 3, wherein the recess terminates at an upper surface of the memory gate and an upper surface of a dummy select gate adjacent to the memory gate, wherein the upper surfaces of the memory gate and dummy select gate are co-planar.

5. The IC of claim 4, wherein the recess is asymmetric with regards to the memory gate and a dummy select gate adjacent to the memory gate.

6. The IC of claim 1, wherein the memory cell gate is a select gate extending over a channel region of the flash memory cell.

7. The IC of claim 6, wherein the recess terminates at an upper surface of the select gate and where the silicide contact pad extends continuously on the upper surface of the select gate between inner sidewalls of the dielectric sidewall spacers.

8. An integrated circuit (IC) for an embedded flash memory device, the integrated circuit comprising:

a semiconductor substrate including;

a memory array region made up of an array of flash memory cells, and a memory contact pad region distinct from the memory array region;

a memory cell gate that extends from a flash memory cell of the array to the memory contact pad region; and

a silicide contact pad arranged over a top surface of the memory cell gate in the memory contact pad region, wherein a top surface of the silicide contact pad in the memory contact pad region is recessed relative to the top surface of the memory cell gate in the memory array region.

9. The IC of claim 8, wherein the silicide contact pad is arranged in a recess within the top surface of the memory cell gate in the memory contact pad region.

10. The IC of claim 9, wherein a dielectric sidewall spacer extends along sidewalls of the recess from an upper surface of the memory cell gate to the top surface of the silicide contact pad at a bottom of the recess.

11. The IC of claim 9, further comprising a vertical contact extending through the recess and coupled to the silicide contact pad at a location in the memory contact pad region.

12. The IC of claim 11, wherein the memory cell gate is a select gate which extends horizontally from the location in the contact pad region to over a channel region of the flash memory cell.

13. The IC of claim 11, wherein the memory cell gate is a memory gate which extends horizontally from the location in the contact pad region to over a channel region of the flash memory cell.

14. The IC of claim 9, wherein the recess terminates at an upper surface of a memory gate and an upper surface of a dummy select gate, wherein the upper surfaces of the memory gate and dummy select gate are co-planar.

15. The IC of claim 14, wherein the recess is asymmetric over the memory gate and a dummy select gate.

16. The IC of claim 8, further comprising:

a logic region arranged in the semiconductor substrate;

a logic device arranged in the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9;

wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate.

17. The integrated circuit according to claim 8, wherein the memory cell gate is one of a memory gate, a select gate, an erase gate, a word line, and a control gate.

18. The integrated circuit according to claim 8, wherein the flash memory device includes:

a select gate;

a memory gate spaced from the memory gate; and

a charge trapping dielectric arranged under the memory gate and between neighboring sidewalls of the select and memory gates.

19. A method for manufacturing an embedded flash memory device, said method comprising:

receiving a semiconductor substrate, which includes a select gate and a memory gate that each extend from a memory array region to a memory contact pad region;

selectively forming recessed regions in the memory contact pad region for the memory gates and select gates;

forming dielectric sidewall spacers on the sidewalls of the recessed regions and on gates of logic devices outside of the memory array region; and

forming nickel silicide on upper surfaces of the memory gate and select gate in the memory contact pad region and concurrently forming a nickel silicide for source/drain regions of the logic devices.

20. The method of claim 19, wherein nickel silicide is formed on source/drain regions of flash cells in the memory array region concurrent with formation of the nickel silicide on the upper surfaces of the memory gate and the select gate.