METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

• US 20160056269A1
• Filed: 06/24/2015
• Published: 02/25/2016
• Est. Priority Date: 08/22/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KOO, Bonyoung, YOO, Jongryeol, LEE, Hyun Jung, KIM, Sunjung, LEE, Seung Hun, TANG, Poren
• Granted Patent: US 9,508,832 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a preliminary channel layer on a substrate including a first region and a second region;

forming a mask pattern on the first region of the substrate to cover the preliminary channel layer;

etching the preliminary channel layer exposed by the mask pattern to form a first channel layer on the first region of the substrate;

forming a second channel layer on the second region of the substrate;

forming a first sacrificial layer on the second channel layer;

performing a surface treatment process on the first sacrificial layer to form a buffer layer in an upper region of the first sacrificial layer, the buffer layer having a bottom surface coplanar with a bottom surface of the mask pattern;

selectively removing the mask pattern and the buffer layer to expose top surfaces of the first sacrificial layer and the first channel layer;

forming a hardmask pattern on the first channel layer and the first sacrificial layer; and

etching the first and second channel layers using the hardmask pattern as an etch mask to form a first channel portion and a second channel portion.

2. The method of claim 1, wherein each of the first and second channel layers is one of a silicon layer and a silicon germanium layer.

3. The method of claim 2, wherein

the substrate is one of a silicon substrate and a silicon germanium substrate, and

the first and second channel layers have a germanium content higher than or equal to that of the substrate.

4. The method of claim 1, wherein

the etching the preliminary channel layer forms the first channel layer having a first thickness T1,

the forming a second channel layer forms the second channel layer having a second thickness T2, and

T1>

T2.

5. The method of claim 4, wherein

the etching the first and second channel layers forms the first channel portion having a top surface at a level lower than that of the first channel layer,

the etching the first and second channel layers forms the second channel portion having a top surface at a same level as that of the second channel layer, and

the top surfaces of the first and second channel portions are formed at a same level.

6. The method of claim 1, wherein the forming a second channel layer forms a silicon-germanium layer using an epitaxial growth process in which a top surface of the substrate is used as a seed layer, and the silicon-germanium layer has a germanium content higher than that of the first channel layer.

7. The method of claim 6, wherein the forming a first sacrificial layer forms the first sacrificial layer having a germanium content lower than that of the second channel layer.

8. The method of claim 1, wherein the forming a first sacrificial layer comprises:

forming the first sacrificial layer using an epitaxial growth process performed continuously after the forming a second channel layer, the first sacrificial layer including a portion protruding upward from the mask pattern; and

polishing the first sacrificial layer to have a top surface coplanar with that of the mask pattern.

9. The method of claim 1, further comprising:

forming a second sacrificial layer on the preliminary channel layer before the forming a mask pattern,

wherein the etching the preliminary channel layer etches the second sacrificial layer and the preliminary channel layer using the mask pattern as an etch mask to form the first channel layer and a second sacrificial layer on the first region of the substrate.

10. The method of claim 9, wherein the forming a second sacrificial layer forms a silicon-germanium layer having a germanium content higher than that of the preliminary channel layer.

11. The method of claim 9, wherein the first and second channel layers are formed to have a same thickness.

12. The method of claim 11, wherein

the etching the first and second channel layers forms the first channel portion to have a top surface at a same level as that of the first channel layer, and

the etching the first and second channel layers forms the second channel portion to have a top surface at a same level as that of the second channel layer.

13. The method of claim 1, wherein the etching the first and second channel layers comprises:

removing the hardmask pattern to expose a top surface of the first sacrificial layer; and

etching the exposed first sacrificial layer to expose top surfaces of the first and second channel portions.

14. A method of fabricating a semiconductor device, comprising:

forming a channel layer on a substrate, the channel layer including silicon germanium;

forming a sacrificial layer on the channel layer, the sacrificial layer including silicon germanium having a germanium content higher than that of the channel layer;

forming a hardmask pattern on the sacrificial layer; and

performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface.

15. The method of claim 14, wherein the forming a channel layer forms the channel layer on the substrate including a silicon germanium layer.

16. A method of fabricating a semiconductor device, comprising:

forming first and second epitaxial layers on respective first and second regions of a substrate, forming a first sacrificial layer on the first epitaxial layer and a second sacrificial layer on the second epitaxial layer, the first sacrificial layer having a germanium content higher than that of the first epitaxial layer and the second sacrificial layer having a germanium content lower than that of the second epitaxial layer; and

etching the first and second sacrificial layers and the first and second epitaxial layers to form a first active fin and a second active fin.

17. The method of claim 16, wherein the etching etches the substrate to form a recess region.

18. The method of claim 17, further comprising:

forming a device isolation layer filling the recess region.

19. The method of claim 16, wherein the forming first and second epitaxial layers forms the first epitaxial layer to have a germanium content different from a germanium content of the second epitaxial layer.

20. The method of claim 16, wherein

the etching forms the first active fin to have a top surface at a same level as that of the first epitaxial layer, and

the etching forms the second active fin to have a top surface at a same level as that of the second epitaxial layer.