Structure and Method and FinFET Device

• US 20160056277A1
• Filed: 08/19/2014
• Published: 02/25/2016
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Wu, Cheng-Hsien, Tsai, Pang-Yen, Lee, Tze-Liang, Ko, Chih-Hsin
• Granted Patent: US 9,276,117 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes The device includes a strain-relaxed buffer (SRB) stack over a substrate, a first fin structure disposed over the SRB stack and a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure.

Claims

1. A device comprising:

a strain-relaxed buffer (SRB) stack over a substrate, the SRB stack including;

a first SRB layer over the substrate;

a dislocation-trap (DisT) layer disposed over the first SRB layer; and

a second SRB layer disposed over the DisT layer;

a first fin structure disposed over the SRB stack, the first fin structure including;

a portion of the second SRB layer;

a first semiconductor material layer disposed over the portion of the second SRB layer; and

a second semiconductor material layer disposed over the first semiconductor material layer; and

a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first fin structure.

2. The device of claim 1, wherein the second semiconductor material layer having the non-uniform width includes an upper portion having a first width and a lower portion having a second width that is different that the first width.

3. The device of claim 2, wherein a ratio of the first width to the second width is in a range of about 75% to about 95%.

4. The device of claim 1, wherein the DisT layer physically contacts the first SRB layer, and

wherein the second SRB layer physically contacts the DisT layer.

5. The device of claim 2, further comprising:

a dielectric layer laterally proximate to the upper portion of the second semiconductor material layer, wherein the lower portion of the second semiconductor material layer is embedded in the dielectric layer.

6. The device of claim 2, wherein the liner is below the upper portion of the second semiconductor material layer in a range of about 25 nm to about 35 nm.

7. The device of claim 1, wherein the first SRB layer and the second SRB layer include a same material, silicon germanium (SiGe_x), here x is Ge composition in atomic percent, wherein x is less than about 50%.

8. The device of claim 1, wherein the DisT layer includes Si layer, having a thickness in a range of about 5 nm to about 30 nm.

9. The device of claim 1, wherein the first semiconductor material layer includes epitaxial silicon (Si), having a thickness in a range of about 30 nm to about 70 nm.

10. The device of claim 1, wherein the second semiconductor material layer includes SiGe_y, y is in a range of about 10% to about 100%.

11. The device of claim 1, wherein the liner includes one or more materials from the group consisting of silicon nitride, silicon oxynitride and aluminum oxide.

12. The device of claim 1, further comprising:

a second fin structure over the SRB stack, the second fin structure including;

the portion of the second SRB layer; and

the first semiconductor material layer disposed over the portion of second SRB layer;

the liner extending along the portion of the second SRB layer and the first semiconductor material layer; and

the dielectric layer laterally proximate to an upper portion of the first semiconductor material layer, wherein a lower portion of the first semiconductor material layer is embedded in the dielectric layer.

13. A fin-like field-effect transistor (FinFET) device comprising:

a strain-relaxed buffer (SRB) stack over a silicon (Si) substrate, the SRB stack including;

a first silicon germanium (SiGe_x) layer over the Si substrate, here x is Ge composition in atomic percent;

a first epitaxial Si layer over the epitaxial SiGe_x layer; and

a second epitaxial SiGe_x layer over the epitaxial Si layer;

a first fin structure over the SRB stack, the first fin structure including;

a portion of the second epitaxial SiGe_x layer;

a second epitaxial Si layer disposed over the portion of the second epitaxial SiGe_x layer; and

a SiGe_y layer disposed over the second epitaxial Si layer, here y is Ge composition in atomic percent, wherein y is larger than x;

a silicon nitride liner extending along the portion of the second SiGe_x layer and a portion of the second epitaxial Si layer; and

a dielectric layer laterally proximate to an upper portion of the SiGe_y layer, wherein a lower portion of the SiGe_y is embedded in the dielectric layer.

14. The device of claim 13, wherein:

x is less than about 50%; and

y is in a range of about 10% to about 100%.

15. The device of claim 13, wherein the first epitaxial Si layer has a thickness in a range of about 5 nm to about 30 nm.

16. The device of claim 13, wherein the SiGe_y layer having the non-uniform width includes an upper portion having a first width and a lower portion having a second width that is different that the first width, wherein a ratio of the first width to the second width is in a range of about 75% to about 95%.

17. The device of claim 13, wherein the first epitaxial Si layer physically contacts the first SiGe_x layer, and

wherein the second SiGe_x layer physically contacts the epitaxial Si layer.

18. The device of claim 13, further comprising:

a second fin structure over the SRB stack, the second fin structure including;

the portion of the second epitaxial SiGe_x layer; and

the second epitaxial Si layer disposed over the portion of the second epitaxial SiGe_x layer;

the silicon nitride liner extending along the portion of the second epitaxial SiGe_x layer and a portion of the second epitaxial Si layer; and

the dielectric layer laterally proximate to an upper portion of the second epitaxial Si layer, wherein a lower portion of the second epitaxial Si layer is embedded in the dielectric layer.

19. A method, comprising:

forming a strain-relaxed buffer (SRB) stack over a substrate, the SRB including;

a first SRB layer over the substrate;

a dislocation-trap (DisT) layer over the first SRB layer; and

a second SRB layer over the DisT layer;

forming first fin structures over the SRB stack, the first fin structure including;

a first epitaxial semiconductor material layer as its upper portion; and

a portion of the second SRB layer as its bottom portion;

forming a liner wrapping along sidewalls of the first fin structure;

forming a dielectric layer over the substrate, including between two adjacent first fin structures;

recessing the upper portion of the first fin structure in a first region while covering the first fin structure in a second region;

epitaxial depositing a second semiconductor material layer over the recessed first fin structure in the first region, to form a second fin structure;

recessing the dielectric layer in both of the first region and the second region to expose upper portions of the first and second fin structures, wherein a portion of the second semiconductor layer is embedded in the recessed dielectric layer; and

trimming upper portions of the first and second fin structure to reduce their width.

20. The method of claim 19, the forming the first fin structure includes:

depositing the first epitaxial semiconductor material layer over the SRB stack; and

etching the first epitaxial semiconductor material layer and the portion of the second SRB layer through a patterned hard mask.