SEMICONDUCTOR DEVICE
First Claim
Patent Images
1. A semiconductor device comprising:
- a p-type semiconductor substrate;
an n-type buried layer formed on the semiconductor substrate;
an n-type semiconductor layer formed on the buried layer;
a floating potential region provided in a part of the semiconductor layer;
a p-type first separation region surrounding the part of the semiconductor layer where the floating potential region is provided, the first separation region being in contact with the semiconductor substrate, and spaced apart from the floating potential region to be formed in a ring-like shape;
a first insulating separation region provided beneath the semiconductor layer between the floating potential region and the first separation region;
a diode formed above the first insulating separation region;
a p-type second separation region spaced apart from the first separation region to surround, in a ring-like shape, a region where the diode is located, and reach beneath the semiconductor layer from a surface of the semiconductor layer;
an n-type source region formed in an upper part of the first separation region; and
an n-type drain contact region of a transistor including the source region, the drain contact region being formed in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region.
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Abstract
In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n−-type buried layer of the semiconductor substrate to use the buried layer beneath the cavity as a drain drift region of the high voltage n-channel MOSFET, whereby a leakage current by holes that flows to the semiconductor substrate side in forward biasing of the bootstrap diode can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a p-type semiconductor substrate; an n-type buried layer formed on the semiconductor substrate; an n-type semiconductor layer formed on the buried layer; a floating potential region provided in a part of the semiconductor layer; a p-type first separation region surrounding the part of the semiconductor layer where the floating potential region is provided, the first separation region being in contact with the semiconductor substrate, and spaced apart from the floating potential region to be formed in a ring-like shape; a first insulating separation region provided beneath the semiconductor layer between the floating potential region and the first separation region; a diode formed above the first insulating separation region; a p-type second separation region spaced apart from the first separation region to surround, in a ring-like shape, a region where the diode is located, and reach beneath the semiconductor layer from a surface of the semiconductor layer; an n-type source region formed in an upper part of the first separation region; and an n-type drain contact region of a transistor including the source region, the drain contact region being formed in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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2. A semiconductor device comprising:
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a p-type semiconductor substrate; an n-type buried layer formed on the semiconductor substrate; an n-type semiconductor layer formed on the buried layer; a floating potential region provided in a part of the semiconductor layer; a p-type first separation region surrounding the part of the semiconductor layer where the floating potential region is provided, the first separation region being in contact with the semiconductor substrate, and spaced apart from the floating potential region to be formed in a ring-like shape; a first insulating separation region provided beneath the semiconductor layer between the floating potential region and the first separation region; a diode formed above the first insulating separation region; a p-type second separation region spaced apart from the first separation region to surround, in a ring-like shape, a region where the diode is located, and reach beneath the semiconductor layer from a surface of the semiconductor layer; a p-type base region formed in an upper part of the semiconductor layer between the first separation region and the second separation region; an n-type source region formed on an upper part of the base region; and an n-type drain contact region of a transistor including the base region and the source region, the drain contact region being formed in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region.
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17. A semiconductor device comprising:
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a p-type semiconductor substrate; an n-type buried layer formed on the semiconductor substrate; a floating potential region provided on the buried layer, a logic circuit being formed in the floating potential region; an n-type semiconductor layer having the same thickness as the floating potential region and located in an island shape on the buried layer so as to surround the floating potential region; a p-type first separation region provided in a ring-like shape so as to surround the semiconductor layer and spaced apart from the floating potential region to reach the semiconductor substrate from an upper surface of the semiconductor layer; a first insulating separation region provided in the buried layer between the floating potential region and the first separation region; a diode formed above the first insulating separation region; a p-type second separation region spaced apart from the first separation region, formed in a ring-like shape so as to surround a part of the semiconductor layer where the diode is located, and passing through the semiconductor layer; an n-type source region of a transistor, the source region being provided on an upper part of the first separation region; and an n-type drain contact region of the transistor, the drain contact region being provided in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region. - View Dependent Claims (19, 20)
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18. A semiconductor device comprising:
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a p-type semiconductor substrate; an n-type buried layer formed on the semiconductor substrate; a floating potential region provided on the buried layer, a logic circuit being formed in the floating potential region; an n-type semiconductor layer having the same thickness as the floating potential region and located in an island shape on the buried layer so as to surround the floating potential region; a p-type first separation region provided in a ring-like shape so as to surround the semiconductor layer and spaced apart from the floating potential region to reach the semiconductor substrate from an upper surface of the semiconductor layer; a first insulating separation region provided in the buried layer between the floating potential region and the first separation region; a diode formed above the first insulating separation region; a p-type second separation region spaced apart from the first separation region, formed in a ring-like shape so as to surround a part of the semiconductor layer where the diode is located, and passing through the semiconductor layer; a p-type base region of a transistor, the base region being formed in an upper part of the semiconductor layer between the first separation region and the second separation region; an n-type source region of the transistor, the source region being formed on an upper part of the base region; and an n-type drain contact region of the transistor, the drain contact region being provided in an upper part of the semiconductor layer between a cathode region of the diode and the floating potential region.
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Specification