HIGH SPEED LEVEL TRANSLATOR

• US 20160056822A1
• Filed: 08/19/2014
• Published: 02/25/2016
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FIFIELD, John A.
• Granted Patent: US 9,503,090 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 19/01742 by means of a pull-up or down element
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence

Abstract

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

Claims

1. A level translator, comprising:

a resistor divider; and

a one-shot circuit in parallel with the resistor divider, and which conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

2. The level translator of claim 1, wherein the resistor divider is switched on/off to provide an output at two different levels VPP2 and VPP.

3. The level translator of claim 2, wherein the one-shot circuit translates from a low voltage to high voltage domain using transistors arranged in parallel with a larger resistor of the resistor divider.

4. The level translator of claim 3, wherein the transistors of the one-shot circuit are provided with a feedback loop to improve switching performance in a direction serviced by a resistor pull up.

5. The level translator of claim 3, wherein the one-shot circuit is comprised of an inverter chain having outputs controlling gates of the transistors which are arranged in series, with one another, to provide a conduction path between an output level to one resistor of the resistor divider.

6. The level translator of claim 1, wherein a 4-level translator circuit translates input signals from Gnd/Vdd to output levels VPP2/VPP where FET voltage stress is limited to Vdd level.

7. The level translator of claim 1, wherein the resistor divider comprises a first resistor R0 and a second resistor R1, in series, which is enabled by transistors T0 and T1, the transistor T1 is a series stack device to limit stress across transistor T0 to Vdd.

8. The level translator of claim 7, wherein resistive values of the resistors R0 and R1 are chosen to output voltage signal V2IN of approximately VPP2 when the transistor T0 receives a Vdd level logic input signal, and when the resistor divider is disabled, the voltage signal V2IN is approximately VPP.

9. The level translator of claim 8, wherein:

the one-shot circuit comprises a pull-up stack comprising two transistors T2 and T3, in series, which allows conduction from VPP to V2IN;

the pull-up stack is enabled during transition of low-to-high switching which increases switching speed; and

the pull-up stack is disabled when low-to-high switching is complete such that a subsequent high-to low transition is unimpeded by the pull-up stack.

10. The level translator of claim 9, wherein the one-shot circuit further comprises an inverter chain comprising inverters.

11. The level translator of claim 10, wherein the inverters are connected in series to establish a pull-up gate signal and its complement to the transistors T2 and T3.

12. A level translator, comprising:

a resistor divider comprising a first resistor and a second resistor, in series; and

a one-shot circuit comprising a first transistor and a second transistor, in series, and in parallel with the resistor divider, and an inverter chain providing control to the first transistor and the second transistor.

13. The level translator of claim 12, wherein the first transistor and the second transistor are controlled to conduct during a transition from a first state to a second state, and non-conduct during a transition from the second state to the first state.

14. The level translator of claim 13, wherein the inverter chain has outputs which control gates of the first transistor and the second transistor.

15. The level translator of claim 14, wherein:

a first output node of the inverter chain is initially at a level so the first transistor is off;

a second output node of the inverter chain is initially at a level so the second transistor is on; and

the one-shot circuit receives an input signal, which is propagated to the first and second output nodes such that a pull-up stack comprising the first transistor and the second transistor pulls up an input voltage by first turning on the first transistor and subsequently turning off the second transistor after the input signal propagates to the second output node.

16. The level translator of claim 15, wherein the first resistor has a larger resistive value than the second resistor and the first resistor is in parallel with the pull-up stack.

17. The level translator of claim 15, wherein the pull-up stack is switched off before an input node is reversed to prevent a slow down on pull-down time.

18. The level translator of claim 15, wherein resistor divider is enabled by transistors T0 and T1.

19. The level translator of claim 18, wherein the transistor T1 is a series stack device to limit stress across transistor T0 to Vdd.

20. A method comprising controlling transistors of a pull-up stack such that the pull-up stack conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.