Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair

• US 20160056827A1
• Filed: 08/20/2015
• Published: 02/25/2016
• Est. Priority Date: 08/20/2014
• Status: Active Grant

• Current Assignee: Short Circuit Technologies Llc
• Original Assignee: Short Circuit Technologies Llc
• Inventors: Vlachogiannakis, Gerasimos S., Ximenes, Augusto Ronchini, Staszewski, Robert Bogdan
• Granted Patent: US 9,722,537 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03B 1/00 Details
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1265 switched capacitors
• CPC Class Codes: H03B 5/1296 the feedback circuit comprising a transformer
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03K 3/015 Modifications of generator to maintain energy constant
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/201 by dithering

Abstract

A novel and useful look-ahead time to digital converter (TDC) that is applied to an all digital phase locked loop (ADPLL) as the fractional phase error detector. The deterministic nature of the phase error during frequency/phase lock is exploited to achieve a reduction in power consumption of the TDC. The look-ahead TDC circuit is used to construct a cyclic DTC-TDC pair which functions to reduce fractional spurs of the output spectrum in near-integer channels by randomly rotating the cyclic DTC-TDC structure so that it starts from a different point every reference clock thereby averaging out the mismatch of the elements. Associated rotation and dithering methods are also presented. The ADPLL is achieved using the look-ahead TDC and/or cyclic DTC-TDC pair circuit.

Claims

1. A cyclic digital to time converter and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit, comprising:

a plurality of controllable delay elements configured in a cyclical sequential chain configuration;

a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing and based thereon to select a starting delay element in said chain, a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC); and

wherein said DTC and TDC elements are dynamically selected.

2. The circuit according to claim 1, wherein said the selection of said DTC and TDC elements is randomized thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.

3. The circuit according to claim 1, wherein said plurality of controllable delay elements comprises a cyclic chain of inverter circuits.

4. The circuit according to claim 1, further comprising a dithering circuit operative to generate FREF dithering.

5. The circuit according to claim 1, further comprising a dithering circuit operative to generate DTC code dithering.

6. A method of cyclic digital to time conversion and time to digital conversion (DTC-TDC) for use in an all digital phase locked loop (ADPLL) circuit, the method comprising:

predicting reference frequency (FREF) clock edge timing and generating a delayed frequency reference clock therefrom;

providing a plurality of controllable delay elements configured in a cyclic sequential chain configuration;

based on the reference frequency clock prediction, selecting at every frequency reference clock a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC); and

dynamically selecting said first number of DTC elements and said second number of TDC elements.

7. The method according to claim 6, further comprising randomly rotating the selection of a starting delay element of the DTC thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.

8. The method according to claim 6, said random rotation is performed every FREF clock cycle.

9. A cyclic digital to time converter and time to digital converter (DTC-TDC) circuit for use in an all digital phase locked loop (ADPLL) circuit, comprising:

a DTC-TDC core circuit incorporating a controllable delay element chain and a phase prediction circuit coupled to a frequency reference (FREF) clock and operative to predict reference frequency clock edge timing;

a DTC encoder-rotator operative to generate an index every FREF cycle and to generate a thermometer DTC code used to select a starting delay element in said chain, a first number of delay elements in said chain to function as a digital to time converter (DTC) and a second number of delay elements in said chain to function as a time to digital converter (TDC);

a TDC decoder operative to determine a marker location from said DTC-DTC core circuit and to convert said location into a phase error fractional portion; and

FREF selection logic output a metastability free delayed version of the FREF clock based on said marker location.

10. The circuit according to claim 9, wherein said DTC encoder-rotator is operative to generate a random index every FREF cycle.

11. The circuit according to claim 9, wherein said marker location comprises either two consecutive zero bits or two consecutive one bits.

12. The circuit according to claim 9, wherein the selection of DTC and TDC elements is randomized thereby scrambling mismatches between said delay elements with a resultant reduction in fractional frequency spurs output by said ADPLL.