RADIOMETRIC TEST AND CONFIGURATION OF AN INFRARED FOCAL PLANE ARRAY AT WAFER PROBE

• US 20160061883A1
• Filed: 08/27/2015
• Published: 03/03/2016
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: Seek Thermal, Inc.
• Original Assignee: Seek Thermal, Inc.
• Inventors: Engberg, Andreas, Parrish, William J.
• Granted Patent: US 9,797,942 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01J 1/08 Arrangements of light sources specially adapted for photometry standard sources, also using luminescent or radioactive material
• CPC Class Codes: G01J 2005/0077 Imaging
• CPC Class Codes: G01J 5/02 Constructional details
• CPC Class Codes: G01J 5/064 Ambient temperature sensor; Housing temperature sensor; Constructional details thereof
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: G01J 5/53 Reference sources, e.g. standard lamps; Black bodies
• CPC Class Codes: G01J 5/80 Calibration using comparison with reference sources G01J5/52
• CPC Class Codes: G01R 31/2656 using non-ionising electromagnetic radiation, e.g. optical radiation
• CPC Class Codes: G01R 31/2832 Specific tests of electronic circuits not provided for elsewhere G01R31/2801, G01R31/316 take precedence
• CPC Class Codes: G01R 31/318511 Wafer Test

Abstract

Disclosed herein are systems and methods for testing FPAs on a wafer prior to dicing the wafer into individual dies. A focal plane array (FPA) can comprise an array of photodetectors, such as microbolometers, on a semiconductor substrate or die. FPAs can be manufactured on a wafer to make multiple FPAs on a single wafer that can be later diced or divided into individual FPAs. Prior to dicing the wafer, the FPAs can be tested electrically and radiometrically in bulk to characterize individual FPAs, to identify bad pixels, to identify bad chips, to calibrate individual FPAs, and the like. These test results can be used to determine acceptable FPAs and can be used to provide initial settings for imaging systems with the tested and integrated FPA.

Claims

1. A method for simultaneously testing a plurality of focal plane arrays on a wafer, each focal plane array on a die on the wafer, the method comprising:

applying electrical voltages to a plurality of dies simultaneously using a probe card having a plurality of sets of probes, individual sets of probes configured to electrically couple to electrical pads on corresponding individual dies on the wafer;

applying electrical voltages to the dies and measuring corresponding electrical voltages to determine the existence of electrical shorts within the die;

controlling components on the plurality of focal plane arrays to have a plurality of tailored values, components of individual focal plane arrays including an adjustable global resistor and adjustable resistor networks;

exposing pixels within the plurality of focal plane arrays to infrared radiation;

acquiring measurements of pixel responses;

adjusting a resistance of at least one of the adjustable global resistor or the adjustable resistor networks to achieve a targeted response for the pixels;

generating a pixel quality table indicating pixels that are flagged as good pixels and pixels that are flagged as bad pixels; and

storing initial adjustment settings for use by an imaging system incorporating one of the plurality of tested focal plane arrays, the initial adjustment settings comprising the adjusted resistance of the adjustable global resistor or the adjustable resistor networks.

2. The method of claim 1 further comprising generating a gain table for pixels in an individual focal plane array based at least in part on the acquired measurements.

3. The method of claim 1, wherein exposing pixels to infrared radiation comprises:

exposing pixels to an infrared emitter at a first temperature; and

exposing pixels to an infrared emitter at a second temperature, hotter than the first temperature.

4. The method of claim 1, wherein the pixel quality table and the determined initial settings are saved to a results data store.

5. The method of claim 4, wherein a thermal imaging system integrating a tested focal plane array die is configured to retrieve the pixel quality table and the determined initial settings from the results data store.

6. The method of claim 1 further comprising configuring a plurality of fuses on an individual die to encode a die identification.

7. The method of claim 6, wherein the pixel quality table or the determined initial settings for an individual focal plane array are stored in a results data store using the die identification to identify the pixel quality table or the determined initial settings associated with the individual focal plane array.

8. The method of claim 1, wherein a tested focal plane array that has been determined to pass performance criteria is suitable for integration in a thermal imager without further testing.

9. The method of claim 1 further comprising classifying a tested focal plane array based on the acquired measurements and the generated pixel quality table.

10. The method of claim 1 further comprising using the acquired measurements and the generated pixel quality table to provide feedback for a wafer manufacturing process.

11. The method of claim 1 further comprising performing a basic communication test with an individual die being tested.

12. The method of claim 1 further comprising performing a bolometer test configured to sample a particular bolometer on a tested die, wherein the sampled data from the particular bolometer is used as an indication of wafer quality.

13. The method of claim 1 further comprising balancing resistor network values so that columns within an individual focal plane array are substantially balanced.

14. The method of claim 1 further comprising testing reference columns of an individual focal plane array to determine a subset of reference columns that are suitable for use during operation as part of a thermal imaging system.

15. The method of claim 1 further comprising repeating at least 1 of the steps with the wafer at more than one ambient temperature.

16. The method of claim 15 wherein the wafer ambient temperature is controlled by a heater in a wafer chuck holding the wafer.

17. The method of claim 16 wherein the die comprises a temperature sensor, and the temperature is calibrated using reading at the plurality of ambient temperature settings.