LATENCY COMMAND PROCESSING FOR SOLID STATE DRIVE INTERFACE PROTOCOL

• US 20160062669A1
• Filed: 08/26/2014
• Published: 03/03/2016
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: BANDIC, Zvonimir Z., VUCINIC, Dejan, GUYOT, Cyril, WANG, Qingbo, CHU, Frank
• Granted Patent: US 9,563,367 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present disclosure relates to methods, apparatuses, systems, and computer program products for processing commands for accessing solid state drives. Example methods can include receiving, from a host, a loaded command availability message. The loaded command availability message can indicate that a command associated with the loaded command availability message uses a low latency mode. The methods can further include executing the associated command.

Claims

1. A method of processing a command for accessing a solid state device, the method comprising:

receiving, from a host, a loaded command availability message, wherein the loaded command availability message indicates that a command associated with the loaded command availability message uses a low latency mode; and

executing the associated command.

2. The method of claim 1, further comprising:

processing a completion of the executed command without generating a traditional interrupt and without writing a completion entry to a normal completion queue on the host; and

upon receiving, from the host, a subsequent command, presuming an acknowledgement by the host of the processed completion.

3. The method of claim 1, further comprising fetching at least one of remaining physical region pages (PRP) and remaining scatter gather lists (SGL) upon a condition that the at least one of the remaining PRP and the remaining SGL exist.

4. The method of claim 1, wherein the loaded command availability message includes fields for at least one of direct memory access (DMA) information, a logical block address (LBA), a completion address, security information, and a length.

5. The method of claim 1, wherein the receiving the loaded command availability message further comprises polling by a latency command processing module substantially periodically and retrieving a remainder of the loaded command availability message for execution.

6. The method of claim 1, further comprising classifying the associated command as at least one of a latency class command and a compact class command.

7. The method of claim 1, wherein the accessing the solid state drive is according to a non-volatile memory express (NVMe) standard modified for latency command processing.

8. A controller comprising:

an interface; and

at least one processor in communication with the interface, the processor configured for;

receiving, over the interface, a loaded command availability message, wherein the loaded command availability message indicates that a command associated with the loaded command availability message uses a low latency mode; and

executing the associated command.

9. The controller of claim 8, wherein the processor is further configured for:

processing a completion of the executed command without generating an interrupt and without writing a completion entry to a normal completion queue on the host; and

upon receiving, over the interface, a subsequent command, presuming an acknowledgement by the host of the processed completion.

10. The controller of claim 8, wherein the processor is further configured for fetching at least one of remaining physical region pages (PRP) and remaining scatter gather lists (SGL) upon a condition that the at least one of the remaining PRP and the remaining SGL exist.

11. The controller of claim 8, wherein the loaded command availability message includes fields for at least one of a direct memory access (DMA) address, a logical block address (LBA), a completion address, security information, a length, a pointer for physical region pages (PRP) and a pointer for scatter gather lists (SGL).

12. The controller of claim 8, wherein the processor configured for receiving the loaded command availability message further comprises the processor configured for polling by a latency command processing module substantially periodically and retrieving a remainder of the loaded command availability message for execution.

13. The controller of claim 8, wherein the processor is further configured for classifying the associated command as at least one of a latency class command and a compact class command.

14. A non-transitory computer program product for processing a command for accessing a solid state device, the computer program product tangibly embodied in a computer-readable medium, the computer program product including instructions operable to cause a data processing apparatus to:

receive a loaded command availability message, wherein the loaded command availability message indicates that a command associated with the loaded command availability message uses a low latency mode;

execute the associated command;

process a completion of the executed command without generating an interrupt and without writing a completion entry to a completion queue on the host; and

upon receiving a subsequent command, presume an acknowledgement by the host of the processed completion.

15. The computer program product of claim 14, further comprising instructions operable to cause the data processing apparatus to:

process a completion of the executed command without generating an interrupt and without writing a completion entry to a normal completion queue on the host; and

upon receiving a subsequent command, presume an acknowledgement by the host of the processed completion.

16. The computer program product of claim 14, further comprising instructions operable to cause the data processing apparatus to fetch at least one of remaining physical region pages (PRP) and remaining scatter gather lists (SGL) upon a condition that the at least one of the remaining PRP and the remaining SGL exist.

17. The computer program product of claim 14, wherein the loaded command availability message includes fields for at least one of a direct memory access (DMA) address, a logical block address (LBA), a completion address, security information, a length, a pointer for physical region pages (PRP) and a pointer for scatter gather lists (SGL).

18. The computer program product of claim 14, wherein the instructions operable to cause the data processing apparatus to receive the loaded command availability message further comprise instructions operable to cause the data processing apparatus to poll using a latency command processing module substantially periodically and retrieve a remainder of the loaded command availability message for execution.

19. The computer program product of claim 14, further comprising instructions operable to cause the data processing apparatus to classify the associated command as at least one of a latency class command and a compact class command.

20. The computer program product of claim 14, wherein the computer program product for accessing the solid state device accesses the solid state device according to a non-volatile memory express (NVMe) standard modified for latency command processing.