SWAP OPERATIONS IN MEMORY

• US 20160062672A1
• Filed: 08/26/2015
• Published: 03/03/2016
• Est. Priority Date: 09/03/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle B.
• Granted Patent: US 9,740,607 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first group of memory cells coupled to a first sense line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second sense line and configured to store a second element. An example apparatus might also include a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.

Claims

1. An apparatus comprising:

a first group of memory cells coupled to a first sense line and configured to store a first element;

a second group of memory cells coupled to a second sense line and configured to store a second element; and

a controller configured to cause the first element to be stored in the second group of memory cells and the second element to be stored in the first group of memory cells by controlling sensing circuitry to perform a number operations without transferring data via an input/output (I/O) line.

2. The apparatus of claim 1, wherein the number of operations comprises a number of AND operations, OR operations, INVERT operations, and SHIFT operations.

3. The apparatus of claim 2, wherein the sensing circuitry comprises a first compute component coupled to the first sense line and formed on pitch with the first group of memory cells and a second compute component coupled to the second sense line and formed on pitch with the second group of memory cells.

4. The apparatus of claim 3, wherein the sensing circuitry comprises a first sense amplifier coupled to the first compute component and a second sense amplifier coupled to the second compute component.

5. The apparatus of claim 4, wherein each of the first and the second sense amplifier comprise a primary latch and each of the first and the second compute component comprises a secondary latch.

6. A method comprising:

performing a swap operation, comprising;

swapping a first element stored in a first group of memory cells coupled to a first sense line and to a number of access lines of an array of memory cells with a second element stored in a second group of memory cells coupled to a second sense line and to the number of access lines, such that subsequent to the swapping, the first element is stored in the second group of memory cells and the second element is stored in the first group of memory cells; and

wherein the swapping is performed without transferring data corresponding to the first and second elements via an input/output (I/O) line.

7. The method of claim 6, wherein, prior to the swapping, the first element is stored as a first bit-vector in the first group of memory cells, with each memory cell in the first group of memory cells storing a respective bit of the first bit-vector.

8. The method of claim 7, wherein, prior to swapping, the second element is stored as a second bit-vector in the second group of memory cells, with each memory cell in the second group of memory cells storing a respective bit of the second bit-vector.

9. The method of claim 8, wherein, subsequent to the swapping, the first bit-vector is stored in the second group of memory cells and the second bit-vector is stored in the first group of memory cells.

10. The method of claim 6, wherein, prior to the swapping:

the first element is stored, as a first bit-vector comprising a number of bits, in a respective number of memory cells of the first group; and

the second element is stored, as a second bit-vector comprising a same number of bits as the first bit-vector, in a respective number of memory cells of the second group; and

wherein bits of the first bit-vector having a same bit position as bits of the second bit-vector are stored in memory cells coupled to a same access line of the number of access lines; and

wherein swapping the first element with the second element comprises swapping bit pairs of the first and second bit-vectors having a same bit position and stored in memory cells coupled to a same access line such that subsequent to the swapping, the first element is stored, as the first bit-vector, in the respective number of memory cells of the second group, and the second element is stored, as the second bit-vector, in the respective number of memory cells of the first group.

11. The method of claim 6, wherein the first element is a first value and the second element is a second value and wherein performing the swap operation results in storing the first value in the second group of memory cells and storing the second value in the first group of memory cells.

12. An apparatus comprising:

a plurality of first groups of memory cells coupled to a plurality of first sense lines and configured to store a plurality of first elements;

a plurality of second groups of memory cells coupled to a plurality of second sense lines and configured to store a plurality of second elements; and

a controller configured to control sensing circuitry to perform a swap operation by storing the plurality of first elements in the plurality of second groups of memory cells and the plurality of second element in the plurality of first groups of memory cells without transferring data via an input/output (I/O) line.

13. The apparatus of claim 12, wherein a quantity of the plurality of first sense lines is a same quantity as a quantity of the plurality of second sense lines.

14. The apparatus of claim 13, wherein each of the plurality of second sense lines is adjacent to a different one of the plurality of first sense lines of a memory array.

15. The apparatus of claim 14, wherein no two of the plurality of second sense lines are adjacent to each other.

16. The apparatus of claim 15, wherein no two of the plurality of first sense lines are adjacent to each other.

17. An apparatus comprising:

a plurality of first groups of memory cells configured to store a plurality of first elements, wherein each group from the plurality of first groups of memory cells is coupled to a different sense line from a plurality of first sense lines and to a number of access lines;

a plurality of second groups of memory cells configured to store a plurality of second elements, wherein each group from the plurality of second groups of memory cells is coupled to a different sense line from a plurality of second sense lines and to the number of access lines; and

a controller configured to control sensing circuitry to, without transferring data via an input/output (I/O) line, swap the plurality of first elements with the plurality of second elements such that the plurality of first elements are stored in the plurality of second groups of memory cells and the plurality of second elements are stored in the plurality of first groups of memory cells.

18. The apparatus of claim 17, wherein the controller is further configured to control the sensing circuitry to perform a number of iterations of operations, and wherein the number of iterations is equal to an element width of the first and the second plurality of elements.

19. The apparatus of claim 18, wherein the first and the second plurality of elements are stored as respective bit-vectors, and wherein the element width is a quantity of bits corresponding to the respective bit-vectors.

20. The apparatus of claim 18, further comprising the controller being configured to control the sensing circuitry to perform each of the number of iterations of operations by storing a particular bit from each of the plurality of first elements in memory cells of the plurality of second groups of memory cells and storing a particular bit from each of the plurality of second elements in memory cells of the plurality of first groups of memory cells.

21. A method for performing a swap operation comprising:

performing, in parallel and without performing a sense line address access, a swap operation in memory on;

a plurality (M) of first elements stored in a plurality of first groups of memory cells, wherein each group of memory cells from the plurality of first groups is coupled to a different sense line from a plurality of first sense lines and to a number (X) of access lines; and

a plurality (M) of second elements stored in a plurality of second groups of memory cells, wherein each group of memory cells from the plurality of second groups is coupled to a different sense line from a plurality of second sense lines and to the X access lines; and

wherein performing the swap operation results in storing the M first elements in the plurality of second groups of memory cells and the M second elements in the plurality of first groups of memory cells.

22. The method of claim 21, wherein each of the M first elements and the M second elements are comprised of a number (N) of bits.

23. The method of claim 22, wherein each of the N bits in each of the M first elements and the M second elements are associated with one of a number (X) of indices corresponding to bit positions of the N bits, and wherein bits from corresponding elements having a same associated index are stored in memory cells that are coupled to a same access line from the X access lines.

24. The method of claim 23, wherein each of the X access lines is associated with a different one of the X indices.

25. The method of claim 24, further comprising, identifying that the swap operation is performed on the plurality of first elements and the plurality of second elements by:

storing a mask bit-vector in a first group of memory cells coupled to a first access line and to a plurality of third sense lines;

wherein the plurality of third sense lines includes the plurality of first sense lines and the plurality of second sense lines; and

storing a shifted mask bit-vector in a second group of memory cells coupled to a second access and to the plurality of third sense lines;

wherein the mask bit-vector and the shifter mask bit-vector identified which elements from the plurality of first elements and the plurality of second elements are used in the swap operation.

26. The method of claim 25, further comprising, performing a number of iterations of operations wherein each iteration of operations is associated with one of the X indices.

27. The method of claim 26, wherein each iteration of operations of the number of iterations of operations further comprises:

storing a first temporary bit-vector that includes a plurality of bits that are associated with a particular index from the X indices from each of the plurality of first elements and the plurality of second elements in a third group of memory cells that are coupled to a third access line and to the plurality of third sense lines; and

storing the first temp bit-vector in a plurality of compute components.

28. The method of claim 27, wherein each iteration of operations of the number of iterations of operations further comprises:

right shifting a bit-vector stored in the plurality of compute components;

performing a first AND operation on the bit-vector and the shifted mask vector; and

storing the result of the first AND operation as a second temp bit-vector in a fourth group of memory cells;

wherein the fourth group of memory cells are coupled to a fourth access line and to the plurality of third sense lines.

29. The method of claim 28, wherein each iteration of operations of the number of iterations of operations further comprise:

storing the shifted mask bit-vector in the plurality of compute components;

performing a first INVERT operation on the bit-vector stored in the plurality of compute components;

performing a second AND operation on the plurality of bits that are associated with the particular index from the X indices from each of the plurality of first elements and the plurality of second elements and on the bit-vector stored in the plurality of compute components;

performing a first OR operation on the result of the second AND operation and on the second temp bit-vector;

storing the result of the first OR operation in memory cells that are coupled to an access line that is associated with the particular index and the X sense lines.

30. The method of claim 29, wherein each iteration of operations of the number of iterations of operations further comprise:

storing the first temp bit-vector in the plurality of compute components;

performing a third AND operation on the bit-vector stored in the plurality of compute components and on the shifted mask vector;

storing the result of the third AND operation in the compute components;

left shifting the bit-vector in the compute component;

storing the bit-vector in the compute components in the fourth group of memory cells.

31. The method of claim 30, wherein each iteration of operations of the number of iterations of operations further comprise:

storing the mask bit-vector in the plurality of compute components;

performing a second INVERT operation on the bit-vector stored in the plurality of compute components;

performing a fourth AND operation on the bit-vector stored in the plurality of compute components and the plurality of bits that are associated with the particular index from the X indices from each of the plurality of first elements and the plurality of second elements;

performing a second OR operation on a result of the fourth AND operation and the second temp bit-vector;

storing a result of the second OR operation in memory cells that are coupled to the access line that is associated with the particular index and the X sense lines.