DIVISION OPERATIONS IN MEMORY

• US 20160062673A1
• Filed: 08/26/2015
• Published: 03/03/2016
• Est. Priority Date: 09/03/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tiwari, Sanjay
• Granted Patent: US 9,747,961 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 7/535 Dividing only
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a dividend element. An example apparatus might include a second group of memory cells coupled to a second access line and configured to store a divisor element. An example apparatus might also include a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

Claims

1. An apparatus comprising:

a first group of memory cells coupled to a first access line and configured to store a dividend element;

a second group of memory cells coupled to a second access line and configured to store a divisor element; and

a controller configured to cause the dividend element to be divided by the divisor element by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line.

2. The apparatus of claim 1, wherein the number of operations comprises a number of AND operations, OR operations, and SHIFT operations.

3. The apparatus of claim 2, wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells.

4. The apparatus of claim 3, wherein the sensing circuitry comprises a sense amplifier and a compute component.

5. The apparatus of claim 4, wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch.

6. A method for performing division operations, comprising:

performing, in parallel and without transferring data via an input/output (I/O) line, a plurality of division operations on;

a plurality of dividend elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and

a plurality of divisor elements stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array; and

providing a plurality of quotient elements and a plurality of remainder elements.

7. The method of claim 6, wherein the plurality of dividend elements are a plurality of first values and the plurality of divisor elements are a plurality of second values.

8. The method of claim 7, wherein the plurality of first values are stored in the first group of memory cells as a dividend bit-vector and the plurality of second values are stored in the second group of memory cells as a divisor bit-vector.

9. The method of claim 8, wherein a number of operations used to perform the plurality of division operations in parallel is the same as a number of operations used to perform any one of the plurality of division operations.

10. An apparatus comprising:

a first group of memory cells coupled to a first access line and configured to store a plurality of dividend elements as bit-vectors;

a second group of memory cells coupled to a second access line and configured to store a plurality of divisor elements as bit-vectors; and

a controller configured to control sensing circuitry to;

perform a plurality of division operations by dividing the plurality of dividend elements by the plurality of divisor elements;

store a plurality of results of the plurality of division operations in a third group of memory cells without transferring data via an input/output (I/O) line; and

wherein the plurality of division operations are performed in parallel.

11. The apparatus of claim 10, wherein the plurality of results comprise a plurality of bit-vectors that represent at least one of a plurality of quotient elements and a plurality of remainder elements.

12. The apparatus of claim 10, wherein the third group of memory cells is a same group of memory cells as at least one of:

the first group of memory cells coupled to the first access line; and

the second group of memory cells coupled to the second access line.

13. The apparatus of claim 10, wherein each of the plurality of division operations is performed on a different element pair including corresponding elements from the plurality of dividend elements and the plurality of divisor elements.

14. A method for dividing elements comprising:

performing a plurality of division operations in parallel on;

a plurality (M) of dividend elements stored in a first group of memory cells coupled to a first access line and to a number (X) of sense lines; and

a plurality (M) of divisor elements stored in a second group of memory cells coupled to a second access line and to the X sense lines;

wherein the plurality of division operations are performed by performing a number of AND operations, OR operations, and SHIFT operations without transferring data via an input/output (I/O) line; and

storing, in parallel and without transferring data via the I/O line, a plurality of results of the division operations in;

a third group of memory cells coupled to a third access line and to the X sense lines; and

a fourth group of memory cells coupled to a fourth access line and to the X sense lines.

15. The method of claim 14, wherein the plurality of results include a plurality (M) of quotient elements stored in the third group of memory cells and a plurality (M) of remainder elements stored in the fourth group of memory cells.

16. The method of claim 15, wherein each of the M dividend elements and the M divisor elements are comprised of N bits.

17. The method of claim 16, wherein each of the N bits in each of the M dividend elements and the M divisor elements are associated with an index and wherein bits from corresponding elements that are associated with a same index are stored in memory cells that are coupled to a same sense line from the X sense lines.

18. The method of claim 17, performing the plurality of division operations in parallel comprises performing the plurality of division operations in parallel using sensing circuitry coupled to the X sense lines.

19. The method of claim 17, further comprising, creating a static mask bit-vector and a dynamic mask bit-vector that identify a most significant bit (MSB) for each of the M dividend elements and the M divisor elements.

20. The method of claim 19, wherein the M dividend elements are stored as a dividend bit-vector, the M divisor elements are stored as a divisor bit-vector, the M quotient elements are stored as a quotient bit-vector, and the M remainder elements are stored as a remainder bit-vector.

21. The method of claim 20, wherein performing the plurality of division operations includes performing a number (E) of iterations of operations.

22. The method of claim 21, wherein each of the E iterations of operations comprises:

storing the dynamic mask bit-vector in the sensing circuitry and in a group of memory cells that store a current dividend bit-vector;

performing a number (P) of iterations of operations comprising;

right shifting the current bit-vector stored in the sensing circuitry;

inverting the right shifted bit-vector in the sensing circuitry;

performing an OR operation on the inverted bit-vector in the sensing circuitry and the static mask bit-vector;

storing the result of the OR operation in the sensing circuitry;

inverting the result of the OR operation in the sensing circuitry;

performing an OR operation on the inverted result in the sensing circuitry and the current dividend bit-vector;

storing the result of the OR operation performed on the inverted result and the current dividend bit-vector in the group of memory cells that store the current dividend bit-vector.

23. The method of claim 22, wherein each of the E iterations of operations further comprises:

performing an AND operation on the result of the OR operation performed on the inverted result and the current dividend bit-vector in the sensing circuitry and the dividend bit-vector;

storing the result of the AND operation in the sensing circuitry and the group of memory cells that store the current dividend bit-vector;

right shifting the result of the AND operation the sensing circuitry;

performing an OR operation on the right shifted bit-vector in the sensing circuitry and on a remainder bit-vector; and

storing the result of the OR operation on the right shifted bit-vector in the sensing circuitry and on the remainder bit-vector in the group of memory cells that store the current dividend bit-vector and in a group of memory cells that store the remainder.

24. The method of claim 23, wherein each of the E iterations of operations further comprises:

performing a comparison operation on the current dividend bit-vector and the divisor bit-vector to determine whether the current dividend bit-vector is greater than or equal to the divisor bit-vector; and

storing the result of the comparison operation in the group of memory cells that store the current compare bit-vector.

25. The method of claim 24, wherein each of the N iterations of operations further comprises right shifting the dynamic mask bit-vector if the current iteration from the P iterations of operations is a second or greater iteration.

26. The method of claim 25, wherein each of the N iterations of operations further comprises:

inverting the current compare bit-vector in the sensing circuitry;

performing an AND operation on the inverted bit-vector in the sensing circuitry and the remainder bit-vector;

storing the result of the AND operation in the current dividend bit-vector; and

storing a difference between the remainder bit-vector and the divisor bit-vector in the memory cells that store the current dividend bit-vector.

27. The method of claim 26, wherein each of the N iterations of operations further comprises:

left shifting the quotient bit-vector in the sensing circuitry;

incrementing elements in the quotient bit-vector based on applying the current compare bit-vector as a mask.

28. The method of claim 27, wherein each of the N iterations of operations comprises:

left shifting the current dividend bit-vector in the sensing circuitry;

storing the left shifted bit-vector in the sensing circuitry in the group of memory cells that store the current dividend bit-vector and a group of memory cells that store the remainder bit-vector.

29. The method of claim 28, wherein each of the N iterations of operations further comprises:

right shifting the dynamic mask bit-vector in the sensing circuitry;

performing an AND operation on the shifted bit-vector in the sensing circuitry and the current compare bit-vector; and

storing the result of the AND operation in the group of memory cells that store the current dividend bit-vector and the sensing circuitry.

30. The method of claim 29, wherein each of the N iterations of operations further comprises:

inverting the current compare bit-vector in the sensing circuitry;

performing an AND operation on the inverted bit-vector in the sensing circuitry and the dynamic mask bit-vector;

performing an OR operation on the result of the AND operation and the current dividend bit-vector; and

storing the result of OR operation in the group of memory cells that store the dynamic mask bit-vector.

31. The method of claim 30, further comprising:

right shifting the remainder bit-vector; and

storing the right shifted remainder bit-vector stored in the sensing circuitry in the memory cells that store the remainder bit-vector.