Process and Apparatus to Reduce Declared Capacity of a Storage Device by Reducing a Range of Logical Addresses

• US 20160062681A1
• Filed: 02/12/2015
• Published: 03/03/2016
• Est. Priority Date: 09/02/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Samuels, Allen, Kruger, Warren Fritz, Truong, Linh Tien
• Granted Patent: US 9,582,203 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/3034 where the computing system component is a storage system, e.g. DASD based or network based digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3442 for planning or managing the needed capacity
• CPC Class Codes: G06F 11/3485 for I/O devices
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a range of logical addresses of a logical address space available to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host.

Claims

1. A method of managing a storage system, the method comprising:

detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system; and

in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a range of logical addresses of a logical address space available to a host.

2. The method of claim 1, further comprising:

prior to detecting the amelioration trigger, detecting a first wear condition of the non-volatile memory of the storage device, wherein a total storage capacity of the non-volatile memory of the storage device includes declared capacity and over-provisioning; and

in response to detecting the first wear condition, performing a remedial action that reduces over-provisioning of the non-volatile memory of the storage device without reducing declared capacity of the non-volatile memory of the storage device.

3. The method of claim 2, wherein detecting the amelioration trigger comprises detecting a second wear condition distinct from the first wear condition.

4. The method of claim 1, wherein the host includes a client on behalf of which data is stored in the storage system.

5. The method of claim 1, wherein the host includes a storage system controller of the storage system.

6. The method of claim 1, wherein the host includes a cluster controller of the storage system.

7. The method of claim 1, wherein the detecting, the performing, or both the detecting and the performing are performed by the storage device.

8. The method of claim 1, wherein the detecting, the performing, or both the detecting and the performing are performed by one or more subsystems of the storage system distinct from the storage device.

9. The method of claim 1, wherein the detecting, the performing, or both the detecting and the performing are performed by the host.

10. The method of claim 1, wherein reducing the range of logical addresses of the logical address space available to the host includes reducing the range of logical addresses of the logical address space available to the host in accordance with one or more parameters for the amelioration process.

11. The method of claim 1, wherein reducing the range of logical addresses of the logical address space available to the host includes removing a contiguous portion of the range of logical addresses of the logical address space available to the host.

12. The method of claim 1, wherein reducing the range of logical addresses of the logical address space available to the host includes moving one or more logical address entries of a mapping table, the mapping table used to translate logical addresses in the logical address space to physical addresses in a physical address space of the storage device.

13. The method of claim 12, wherein moving one or more logical address entries of the mapping table includes moving the one or more logical address entries without moving data stored at the one or more physical addresses associated with the one or more logical address entries.

14. The method of claim 12, including, prior to moving the one or more logical address entries of the mapping table, selecting the one or more logical address entries to be moved so as to minimize performance degradation.

15. The method of claim 12, including, prior to moving the one or more logical address entries of the mapping table, selecting the one or more logical address entries to be moved so as to minimize overhead from garbage collection.

16. The method of claim 12, including, prior to moving the one or more logical address entries of the mapping table, selecting the one or more logical address entries to be moved so as to minimize a number of logical address entries to move.

17. The method of claim 1, wherein performing the amelioration process to reduce declared capacity of the non-volatile memory of the storage device further includes advertising a reduced declared capacity of the non-volatile memory of the storage device.

18. The method of claim 1, further comprising:

after beginning performance of the amelioration process to reduce declared capacity of the non-volatile memory of the storage device, detecting an indication to abort the reduction in declared capacity of the non-volatile memory of the storage device; and

in response to detecting the indication to abort the reduction in declared capacity of the non-volatile memory of the storage device, aborting performance of the amelioration process to reduce declared capacity of the non-volatile memory of the storage device.

19. The method of claim 1, wherein performing the amelioration process to reduce declared capacity of the non-volatile memory of the storage device includes reducing utilization of the non-volatile memory of the storage device.

20. The method of claim 1, wherein reducing the range of logical addresses of the logical address space available to the host includes copying data stored at a first set of physical addresses associated with a first set of logical address entries in a mapping table to a second set of physical addresses associated with a second set of logical address entries in the mapping table, and updating the first set of logical address entries in the mapping table, the mapping table used to translate logical addresses in the logical address space to physical addresses in a physical address space of the storage device.

21. The method of claim 20, wherein updating the first set of logical address entries in the mapping table includes invalidating one or more logical address entries of the first set of logical address entries.

22. The method of claim 1, wherein the storage device comprises one or more flash memory devices.

23. A storage device, comprising:

non-volatile memory;

one or more processors; and

controller memory storing one or more programs, which when executed by the one or more processors cause the storage device to perform operations comprising;

detecting an amelioration trigger for reducing declared capacity of the non-volatile memory of the storage device;

performing, in accordance with the detected amelioration trigger, an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a range of logical addresses of a logical address space available to a host.

24. The storage device of claim 23, wherein the one or more programs further include instructions that, when executed by the one or more processors, cause the storage device to perform operations comprising:

prior to detecting the amelioration trigger, detecting a first wear condition of the non-volatile memory of the storage device, wherein a total storage capacity of the non-volatile memory of the storage device includes declared capacity and over-provisioning; and

in response to detecting the first wear condition, performing a remedial action that reduces over-provisioning of the non-volatile memory of the storage device without reducing declared capacity of the non-volatile memory of the storage device.

25. A non-transitory computer readable storage medium, storing one or more programs configured for execution by one or more processors of a storage device, the one or more programs including instructions for:

detecting an amelioration trigger for reducing declared capacity of non-volatile memory of the storage device; and

in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a range of logical addresses of a logical address space available to a host.

26. The non-transitory computer readable storage medium of claim 25, wherein the one or more programs further include instructions for:

prior to detecting the amelioration trigger, detecting a first wear condition of the non-volatile memory of the storage device, wherein a total storage capacity of the non-volatile memory of the storage device includes declared capacity and over-provisioning; and

in response to detecting the first wear condition, performing a remedial action that reduces over-provisioning of the non-volatile memory of the storage device without reducing declared capacity of the non-volatile memory of the storage device.