SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME

• US 20160062686A1
• Filed: 01/08/2015
• Published: 03/03/2016
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Hee Youl
• Granted Patent: US 9,691,494 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A semiconductor device and a method of operating the same are provided. A plurality of memory blocks are erased. It is determined whether a selected memory block among the memory blocks is a lastly erased memory block. The selected memory block or another memory block is programmed according to a result of determination.

Claims

1. A method of operating a semiconductor device, comprising:

erasing memory blocks;

determining whether a selected memory block among the memory blocks is a lastly erased memory block; and

programming the selected memory block or another memory block according to a result of determination.

2. The method of claim 1, wherein the erasing of the memory blocks comprises:

sequentially erasing the memory blocks; and

marking the lastly erased memory block.

3. The method of claim 2, wherein the marking of the lastly erased memory block programs marking data on a flag cell of the lastly erased memory block.

4. The method of claim 3, wherein it is determined whether the selected memory block among the memory blocks is the lastly erased memory block based on the marking data.

5. The method of claim 4, wherein the marking data has a value of ‘

0’

indicating the lastly erased memory block, or a value of ‘

1’

indicating a memory block other than the lastly erased memory block.

6. The method of claim 1,

wherein the memory blocks include one or more hidden memory blocks, and

wherein the erasing erases two or more memory blocks including the hidden memory blocks.

7. The method of claim 6, wherein the erased memory block is determined to be the lastly erased memory block when the number of the erased memory blocks other than the hidden memory block is one.

8. The method of claim 7, wherein the program operation is performed on the hidden memory block when the lastly erased memory block is the only remaining programmable memory block.

9. The method of claim 8, further comprising, after the program operation of the hidden memory block is completed, copying the programmed data of the hidden memory blocks back into the lastly erased memory block.

10. The method of claim 9, further comprising, after the copying of the data back into the erased memory block, marking the lastly erased memory block as a programmed memory block after the copying.

11. The method of claim 10, wherein the marking of the lastly erased memory block programs marking data on a flag cell of the lastly erased memory block.

12. The method of claim 11, wherein the lastly erased memory block having the marking data is free from a subsequent program operation.

13. A semiconductor device comprising:

a cell array including memory blocks, one or more of which are hidden memory blocks;

a peripheral circuit suitable for performing an erase operation and a program operation on the memory blocks; and

a control circuit suitable for controlling the peripheral circuit to erase memory blocks, and determine whether a selected memory block among the memory blocks is a lastly erased memory block, and program the selected memory block or another memory block according to a result of determination.

14. The semiconductor device of claim 13, wherein each of the memory blocks comprises memory cells having a charge trap layer structure.

15. The semiconductor device of claim 13, wherein the control circuit controls the peripheral circuit to mark the lastly erased memory block among the memory blocks.

16. The semiconductor device of claim 15, wherein the control circuit controls the peripheral circuit to program a marking data on a flag cell of the lastly erased memory block.

17. The semiconductor device of claim 16, wherein the control circuit identifies the lastly erased memory block based on the marking data.

18. The semiconductor device of claim 13,

wherein the control circuit identifies the lastly erased memory block from the selected memory blocks other than the hidden memory blocks, and

wherein the control circuit controls the peripheral circuit to perform the program operation on the hidden memory blocks when the lastly erased memory block is the only remaining programmable memory block.

19. The semiconductor device of claim 18, wherein the control circuit controls the peripheral circuit to copy the programmed data of the hidden memory blocks into the lastly erased memory block.

20. The semiconductor device of claim 19, wherein the control circuit controls the peripheral circuit to mark the lastly erased memory block as a programmed memory block after the copying.

21. The semiconductor device of claim 20, wherein the control circuit controls the peripheral circuit to program a marking data on a flag cell of the lastly erased memory block.