SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF

• US 20160062827A1
• Filed: 08/28/2014
• Published: 03/03/2016
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Yamauchi, Kazuki
• Granted Patent: US 10,395,753 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/403 Error protection encoding, e.g. using parity or ECC codes
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit.

Claims

1. A semiconductor memory device, comprising:

a memory array;

a data keeping element, keeping data read from the memory array or keeping data written to the memory array;

an error checking correction (ECC) element, performing error checking and correction of data;

a transferring element, transferring data from the data keeping element to the ECC element;

a writing element, writing an ECC code generated by the ECC element to the data keeping element; and

a detecting element, detecting whether data inputted to the data keeping element has a specific bit string;

wherein when the specific bit string is detected, the transferring element forbids transfer of data corresponding to the specific bit string, and the writing element writes a predetermined ECC code to the data keeping element.

2. The semiconductor memory device of claim 1, wherein the specific bit string is a bit string in which all bits are logic 0.

3. The semiconductor memory device of claim 1, wherein the specific bit string is a bit string in which all bits are logic 1.

4. The semiconductor memory device of claim 1, wherein the specific bit string has a number of bits equal to a number of bits transferred simultaneously by the transferring element.

5. The semiconductor memory device of claim 1, wherein the data keeping element is divided into a plurality of sectors, the transferring element transfers the data in units of sectors, and the ECC element performs an ECC process in units of sectors.

6. The semiconductor memory device of claim 1, wherein a number of bits of the specific bit string is equal to a number of bits of a page kept by the data keeping element.

7. The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a memory element storing a relationship between the specific bit string and the ECC code, and the writing element writes the ECC code for the specific bit string based on a detection result of the detecting element.

8. The semiconductor memory device of claim 1, wherein the writing element comprises a logic circuit generating the ECC code for the specific bit string based on a detection result of the detecting element, and writes the ECC code generated by the logic circuit.

9. The semiconductor memory device of claim 1, wherein the semiconductor memory device comprises a plurality of external input/output terminals, data inputted from the plurality of external input/output terminals are loaded in parallel to the data keeping element, and the detecting element detects whether the data inputted in parallel contains the specific bit string.

10. The semiconductor memory device of claim 1, wherein the memory array is a NAND memory array and the data keeping element comprises a page buffer.

11. A programming method, the programming method being a programming method of a NAND flash memory, wherein the method comprises:

loading programming data inputted from an external input/output terminal to a page buffer,

detecting whether the programming data is a specific bit string,

when detecting that the programming data is not the specific bit string, transferring the programming data kept by the page buffer to an error checking correction (ECC) circuit, and writing an ECC code generated by an ECC operation to the page buffer, and

when detecting that the programming data is the specific bit string, forbidding transfer of the programming data kept by the page buffer, and writing a known ECC code corresponding to the specific bit string to the page buffer.

12. The programming method of claim 11, wherein the programming data is a bit string in which all bits are logic 0.

13. The programming method of claim 11, wherein the programming date is a bit string in which all bits are logic 1.