SEMICONDUCTOR MEMORY DEVICE

• US 20160062829A1
• Filed: 01/29/2015
• Published: 03/03/2016
• Est. Priority Date: 08/29/2014
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: HARASAWA, Akinori, MORO, Hiroyuki
• Application Number:
  US14/608,715
• Publication Number:
  US 20160062829A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/2903 Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence

Abstract

According to one embodiment, a semiconductor memory device includes a generator to generate an error correction code. The generator includes a first encoder to calculate a first error correction code, a second encoder to calculate a second correction code, and an operation part to operate the first error correction code and the second error correction code.

Claims

1. A semiconductor memory device, comprising:

a nonvolatile memory system; and

a generator to generate an error correction code;

the generator including,

a first encoder to calculate a first error correction code with respect to a first data to be encoded,

a second encoder to calculate, if the first data is unencodable, a second error correction code with respect to a third data generated from a second data corresponding to the first data, which is read from the nonvolatile memory system, and

an operation part to operate the first error correction code and the second error correction code, and wherein

the generator generates an operation result of a predetermined unit from the operation part as the error correction code.

2. The semiconductor memory device of claim 1, further comprising:

a controller to read and write a data received from the nonvolatile memory system through a plurality of channels;

a first path to read a data from a predetermined number of channels in the plurality of channels and transfer the data to the first encoder; and

a second path to read a data from channels remaining in the plurality of channels excluding the predetermined number of channels and transfer the data to the second encoder.

3. The semiconductor memory device of claim 2, further comprising a buffer to merge the first data and the second data corresponding to the first data read from the nonvolatile memory system together, the buffer to compensate the first data with the second data corresponding to the first data to generate the third data encodable.

4. The semiconductor memory device of claim 1, wherein the operation part performs operation for acquiring exclusive OR.

5. The semiconductor memory device of claim 1, wherein the first data to be encoded is received from a host system.

6. The semiconductor memory device of claim 1, wherein the first data to be encoded is a garbage collection data.

7. The semiconductor memory device of claim 1, comprising a first buffer to transfer the first error correction code received from the first encoder to the operation part and to transfer the first error correction code to the first encoder and a second buffer to transfer the second error correction code received from the second encoder to the operation part and to transfer the second error correction code to the second encoder.

8. The semiconductor memory device of claim 1, further comprising a timing controller to control a timing of input of the first error correction code and the second error correction code to the operation part to be simultaneous.

9. The semiconductor memory device of claim 8, further comprising an interface to be connected with a host system, wherein

the timing controller controls the timing when the data received from the host system through the interface are unencodable.

10. A semiconductor memory device comprising a generator to generate an error correction code, the generator including a first encoder to calculate a first error correction code, a second encoder to calculate a second error correction code, and an operation part to operate exclusive OR from the first error correction code and the second error correction code, wherein the generator generates an operation result from the operation part as the error correction code.

11. A semiconductor memory device comprising a generator to generate an error correction code, the generator including a first encoder to calculate a first error correction code, a second encoder to calculate a second error correction code, and an operation part to operate the first error correction code and the second error correction code.