MEMORY SYSTEM
First Claim
1. A memory system comprising:
- a memory controller which executes a data access process with an external using an access unit;
a first memory which is connected to the memory controller via a bus and has a first latency; and
a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency;
wherein the access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory, andthe memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size.
2 Assignments
0 Petitions
Accused Products
Abstract
A memory system includes: a memory controller which executes a data access process with an external using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size.
18 Citations
18 Claims
-
1. A memory system comprising:
-
a memory controller which executes a data access process with an external using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency; wherein the access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory, and the memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
Specification