SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND SYSTEM ON CHIP

• US 20160062913A1
• Filed: 07/06/2015
• Published: 03/03/2016
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Deum-Ji Woo, Kwan-Ho Kim, Mi-Kyung Kim
• Inventors: KIM, Kwan-Ho, WOO, Deum-Ji, KIM, Mi-Kyung, LEE, Beom-Woo
• Granted Patent: US 9,904,626 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure

Abstract

At least one example embodiment discloses a semiconductor device including a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, wherein the DMA system includes an initializer configured to set a data transfer parameter for writing the first data to the memory during a flushing period of second data from a cache to the address by a processor, a creator configured to create the first data based on the set data transfer parameter, and a transferer configured to write the first data to the address of the memory after the flushing period based on the data transfer parameter.

Claims

1. A semiconductor device comprising:

a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, the DMA system including,

an initializer configured to set a data transfer parameter for writing the first data to the memory during a flushing period of second data from a cache to the address by a processor;

a creator configured to create the first data based on the set data transfer parameter; and

a transferer configured to write the first data to the address of the memory after the flushing period based on the data transfer parameter.

2. The semiconductor device of claim 1, wherein the first data is different from the second data.

3. The semiconductor device of claim 1, wherein the creator is configured to one of receive the first data from an external device and directly create the first data.

4. The semiconductor device of claim 3, wherein the creator is configured to perform at least one of a read operation and a write operation on the external device.

5. The semiconductor device of claim 1, further comprising:

a buffer configured to store the first data.

6. The semiconductor device of claim 5, wherein the creator is configured to store the first data in the buffer.

7. The semiconductor device of claim 6, wherein the transferer is configured to transfer the first data stored in the buffer to the memory.

8. The semiconductor device of claim 5, wherein the data transfer parameter includes a size of the first data, an address of the buffer storing the first data, and the address of the memory.

9. The semiconductor device of claim 1, wherein the initializer is configured to receive information related to the data transfer parameter and information related to flushing of the cache from the processor.

10. The semiconductor device of claim 9, wherein the transferer is configured to receive the information related to the flushing of the cache from the initializer and be disabled during the flushing period.

11-22. -22. (canceled)

23. A semiconductor device comprising:

a direct memory access (DMA) system configured to directly access a memory; and

a buffer configured to store first data and second data to be transferred to the memory, wherein the DMA system includes;

an initializer configured to set a data transfer parameter for transferring the first data and the second data to the memory during a flushing period of third data from a cache to a first address of the memory;

a creator configured to sequentially perform a first creation and a second creation, the creator configured to perform the first creation by creating the first data based on the data transfer parameter and storing the first data in the buffer during the flushing period and the creator configured to perform the second creation by creating the second data and storing the second data in the buffer; and

a transferer configured to sequentially perform a first transfer and a second transfer, the transferer configured to perform the first transfer such that the first data stored in the buffer is transferred to the first address of the memory after the flushing period and during the second creation based on the data transfer parameter, and the transferer configured to the second transfer such that the second data stored in the buffer is transferred to a second address of the memory.

24-47. -47. (canceled)

48. A memory system comprising:

a memory;

a processor configured to flush first data in a cache to an address of the memory during a flushing period; and

a direct memory access system, the direct memory access system including,

an initializer configured to operate during the flushing period and create second data, and

a transferer configured to transfer the second data to the address of the memory outside of the flushing period.

49. The memory system of claim 48, wherein the initializer is configured to generate a data transfer parameter during the flushing period and the transferer is configured to transfer the second data based on the data transfer parameter.

50. The memory system of claim 49, wherein the transferer is configured to transfer the second data to the address after the flushing period.

51. The memory system of claim 48, wherein the memory system is configured to disable the transferer before the flushing period.

52. The memory system of claim 48, wherein the memory system is configured to enable the transferer when the flushing period ends.

53. The memory system of claim 48, wherein the memory comprises a three-dimensional memory array.

54. The memory system of claim 53, wherein the three-dimensional memory comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

55. The memory system of claim 53, wherein the three dimensional memory array comprises a plurality of memory cells, each of the memory cells including a charge trap layer.

56. The memory system of claim 53, wherein at least one of word lines and bit lines in the three-dimensional memory array are shared between levels.