ARRAYS WITH COMPACT SERIES CONNECTION FOR VERTICAL NANOWIRES REALIZATIONS

• US 20160063163A1
• Filed: 08/25/2015
• Published: 03/03/2016
• Est. Priority Date: 08/26/2014
• Status: Abandoned Application

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Moroz, Victor, Kawa, Jamil
• Application Number:
  US14/834,780
• Publication Number:
  US 20160063163A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06F 2111/14 related to nanotechnology
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

An integrated circuit design tool includes a functional cell library. An entry in the cell library comprises a specification of the cell. Entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library comprising a specification of a cell including a plurality of transistors and an interconnect. At least two transistors in the plurality are in series via at least the interconnect. The transistors and the interconnect can be vertically oriented to support vertical current through a vertical channel relative to the substrate.

Claims

1. A computer system adapted to process a computer implemented representation of a circuit design, comprising:

a processor and a memory coupled to the processor, the memory storing processor readable parameters specifying structural features of a physical implementation of a circuit, the circuit including;

a plurality of nanowire transistors; and

a nanowire interconnect,

wherein at least two nanowire transistors in the plurality are electrically in series via at least the nanowire interconnect.

2. The computer system of claim 1, wherein said at least two transistors are oriented vertically relative to a substrate, and further comprising:

a conductor electrically connecting a source terminal of a first transistor of said at least two transistors and a drain terminal of a second transistor of said at least two transistors.

3. The computer system of claim 2, wherein said first transistor and said second transistor are a same conductivity type.

4. The computer system of claim 1, wherein the nanowire interconnect has an opposite conductivity type in contrast with said first vertical nanowire transistor and said second vertical nanowire transistor.

5. The computer system of claim 1, wherein said at least two nanowire transistors include a first vertical nanowire transistor and a second vertical nanowire transistor both being n-type transistors, and said nanowire interconnect is a first vertical nanowire electrically connecting a first drain of the first vertical nanowire transistor with a first source of the second vertical nanowire transistor.

6. A computer program product, comprising:

a memory device having stored thereon a computer readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the circuit including;

a plurality of nanowire transistors; and

a nanowire interconnect,

wherein at least two nanowire transistors in the plurality are electrically in series via at least the nanowire interconnect.

7. The computer program product of claim 6, wherein said at least two transistors are oriented vertically relative to a substrate, and further comprising:

a conductor electrically connecting a source terminal of a first transistor of said at least two nanowire transistors and a drain terminal of a second nanowire transistor of said at least two nanowire transistors.

8. The computer program product of claim 7, wherein said first transistor and said second transistor are a same conductivity type.

9. The computer program product of claim 6, wherein the nanowire interconnect has an opposite conductivity type in contrast with said first vertical nanowire transistor and said second vertical nanowire transistor.

10. The computer program product of claim 6, wherein said at least two nanowire transistors include a first vertical nanowire transistor and a second vertical nanowire transistor both being n-type transistors, and said nanowire interconnect is a first vertical nanowire electrically connecting a first drain of the first vertical nanowire transistor with a first source of the second vertical nanowire transistor.

11. A computer program product, comprising:

a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the circuit including;

an array of circuit cells, the circuit cells including a plurality of nanowire transistors and a vertical nanowire interconnect,

wherein the plurality of nanowire transistors includes;

a first vertical nanowire transistor including;

a first gate at a first intermediate height in between a first source at a first source height and a first drain at a first drain height;

a second vertical nanowire transistor including;

a second gate at a second intermediate height in between a second source at a second source height and a second drain at a second drain height;

wherein the vertical nanowire interconnect traverses the first intermediate height of the first vertical nanowire transistor, and traverses the second intermediate height of the second vertical nanowire transistor, to electrically couple in series the first vertical nanowire transistor and the second vertical nanowire transistor.

12. The computer program product of claim 11, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are a same conductivity type.

13. The computer program product of claim 11, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are a same conductivity type, and the vertical nanowire interconnect has an opposite conductivity type in contrast with said first vertical nanowire transistor and said second vertical nanowire transistor.

14. The computer program product of claim 11, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are n-type transistors, and said first vertical nanowire electrically connects the first drain of the first vertical nanowire transistor with the first source of the second vertical nanowire transistor.

15. The computer program product of claim 11, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are a same conductivity type, and

wherein the circuit further comprises:

a third vertical nanowire transistor and a fourth vertical nanowire transistor having an opposite conductivity type in contrast with said first vertical nanowire transistor and said second vertical nanowire transistor;

a first conductor electrically connecting the first gate of the first vertical nanowire transistor with a third gate of the third vertical nanowire transistor; and

a second conductor electrically connecting the second gate of the second vertical nanowire transistor with a fourth gate of the fourth vertical nanowire transistor,

wherein the first conductor and the second conductor are different electrical inputs of a NAND gate.

16. A computer system adapted to process a computer implemented representation of a circuit design, comprising:

a processor and a memory coupled to the processor, the memory storing including processor readable parameters specifying structural features of a physical implementation of a circuit;

the circuit including;

an array of circuit cells, the circuit cells including a plurality of nanowire transistors and a vertical nanowire interconnect,

wherein the plurality of nanowire transistors includes;

a first vertical nanowire transistor including;

a first gate at a first intermediate height in between a first source at a first source height and a first drain at a first drain height; and

a second vertical nanowire transistor including;

a second gate at a second intermediate height in between a second source at a second source height and a second drain at a second drain height,

wherein the vertical nanowire interconnect traverses the first intermediate height of the first vertical nanowire transistor, and traverses the second intermediate height of the second vertical nanowire transistor, to electrically couple in series the first vertical nanowire transistor and the second vertical nanowire transistor.

17. The computer system of claim 16, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are a same conductivity type.

18. The computer system of claim 16, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are a same conductivity type, and the vertical nanowire interconnect has an opposite conductivity type in contrast with said first vertical nanowire transistor and said second vertical nanowire transistor.

19. The computer system of claim 16, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are n-type transistors, and said first vertical nanowire electrically connects the first drain of the first vertical nanowire transistor with the first source of the second vertical nanowire transistor.

20. The computer system of claim 16, wherein said first vertical nanowire transistor and said second vertical nanowire transistor are a same conductivity type,

wherein the circuit further comprises:

a third vertical nanowire transistor and a fourth vertical nanowire transistor having an opposite conductivity type in contrast with said first vertical nanowire transistor and said second vertical nanowire transistor;

a first conductor electrically connecting the first gate of the first vertical nanowire transistor with a third gate of the third vertical nanowire transistor; and

a second conductor electrically connecting the second gate of the second vertical nanowire transistor with a fourth gate of the fourth vertical nanowire transistor,

wherein the first conductor and the second conductor are different electrical inputs of a NAND gate.