MULTIPLICATION OPERATIONS IN MEMORY

• US 20160063284A1
• Filed: 08/24/2015
• Published: 03/03/2016
• Est. Priority Date: 09/03/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tiwari, Sanjay
• Granted Patent: US 9,904,515 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 7/523 Multiplying only
• CPC Class Codes: G06F 7/53 in parallel-parallel fashion, i.e. both operands being entered in parallel G06F7/533 takes precedence
• CPC Class Codes: G06G 7/16 for multiplication or division G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

Examples of the present disclosure provide apparatuses and methods for performing multi-variable bit-length multiplication operations in a memory. An example method comprises performing a multiplication operation on a first vector and a second vector. The first vector includes a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array. The second vector includes a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The example multiplication operation can include performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

Claims

1. A method for performing multiplication operations comprising:

performing a multiplication operation on;

a first vector comprising a number of first elements stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array; and

a second vector comprising a number of second elements stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array;

wherein the multiplication operation includes performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line.

2. The method of claim 1, wherein performing the number of AND operations, OR operations and SHIFT operations without transferring data via an I/O line comprises performing the number of AND operations, OR operations and SHIFT operations without a sense line address access.

3. The method of claim 1, further comprising storing a result of the multiplication operation is in a group of memory cells coupled to a third access line.

4. The method of claim 1, further comprising storing a result of the multiplication operation in at least one of the group of memory cells coupled to the first access line and the group of memory cells coupled to the second access line.

5. The method of claim 1, wherein performing the number of AND, OR and SHIFT operations comprises performing the number of AND, OR and SHIFT operations using sensing circuitry coupled to the memory cells.

6. The method of claim 5, wherein performing the number of AND, OR and SHIFT operations using sensing circuitry comprises performing the number of AND, OR and shift operations using sense amplifiers and compute components, wherein the sense amplifiers and compute components each comprise a respective number of transistors formed on pitch with the memory cells.

7. The method of claim 1, wherein performing the multiplication operations comprises performing a number of iterations of operations, wherein each iteration of the number of operations comprises determining a data value contribution corresponding to a respective bit position of each of the number of first elements and each of the number of second elements.

8. The method of claim 1, further comprising storing a first element and a second element of the first vector in the group of memory cells coupled to the first access line.

9. The method of claim 8, further comprising storing a third element and a fourth element of the second vector in the group of memory cells coupled to the second access line.

10. The method of claim 9, wherein the first element and the third element have a first bit length and the second element and the fourth element have a second bit length.

11. An apparatus comprising:

a first group of memory cells coupled to a first access line and configured to store a first element;

a second group of memory cells coupled to the first access line and configured to store a second element;

a third group of memory cells coupled to a second access line and configured to store a third element; and

a fourth group of memory cells coupled to the second access line and configured to store a fourth element; and

a controller configured to control sensing circuitry to multiply the first element by the third element and to multiply the second element by the fourth element by performing a number of operations without transferring data via an input/output (I/O) line,

wherein the first element and the third element are a first bit-length and the second element and the fourth element are a second bit-length.

12. The apparatus of claim 11, wherein the number of operations comprises a number of AND operations, OR operations and SHIFT operations.

13. The apparatus of claim 11, wherein the controller is further configured to control the sensing circuitry to determine a least-significant bit of the first, second, third, and fourth elements.

14. The apparatus of claim 11, wherein the controller is further configured to control the sensing circuitry to determine a most-significant bit of the first, second, third and fourth elements.

15. The apparatus of claim 11, comprising a fifth group of memory cells coupled to a third access line, wherein the controller is configured to cause a result of multiplying the first element by the third element and a result of multiplying the second element by the fourth element to be stored in the fifth group of memory cells.

16. The apparatus of claim 11, wherein the first and the third group of memory cells are coupled to a first number of sense lines and the second and the fourth group of memory cells are coupled to a second number of sense lines.

17. The apparatus of claim 16, wherein the first number of sense lines are different than the second number of sense lines.

18. The apparatus of claim 11, wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells.

19. The apparatus of claim 11, wherein the first bit-length and the second bit-length are different bit-lengths.

20. A method for performing multi-variable bit-length multiplication operations comprising:

performing a multiplication operation on;

a first element with a first bit-length stored in a first group of memory cells coupled to a first access line and a first number of sense lines of a memory array;

a second element with a second bit-length stored in a second group of memory cells coupled to the first access line and to a second number of sense lines of the memory array;

a third element with the first bit-length stored in a third group of memory cells coupled to a second access line and the first number of sense lines of the memory array; and

a fourth element with the second bit-length stored in a group of memory cells coupled to the second access line and the second number of sense lines of the memory array;

wherein performing the multiplication operation includes performing a number of AND operations, OR operations and SHIFT operations without transferring data via an input/output (I/O) line; and

storing a result of the multiplication operation as a fifth element and a sixth element in a group of memory cells coupled to a third access line.

21. The method of claim 20, wherein performing the multiplication operation comprises performing a number of iterations of operations using a dynamic mask element and a static mask element, wherein each iteration of the number of operations comprises determining a data value contribution corresponding to a respective bit position of the first, the second, the third, and the fourth elements.

22. The method of claim 21, wherein a first iteration of the number of iterations of operations comprises determining a data value contribution corresponding to a first bit position of the first, the second, the third, and the fourth elements to a multiplication result.

23. The method of claim 22, wherein a second iteration of the number of iterations of operations comprises determining a data value contribution corresponding to a second bit position of the first, the second, the third, and the fourth elements.

24. The method of claim 22, wherein the dynamic mask indicates a least significant bit (LSB) position for the first, the second, the third, and the fourth element during the first iteration.

25. The method of claim 21, wherein performing the multiplication operation comprises determining the static mask element.

26. The method of claim 27, wherein the static mask element is determined prior to an iteration of operations during the performance of the multiplication operation.

27. The method of claim 24, wherein the static mask element is determined by:

loading an element indicating a most significant bit for each of the first, the second, the third, and the fourth elements into the sensing circuitry; and

inverting the element indicating the most significant bit.

28. An apparatus comprising:

a first number of memory cells coupled to a number of sense lines and to a first access line, wherein the first number of memory cells are configured to store a first number of elements and the first number of elements include at least two element bit-lengths;

a second number of memory cells coupled to the number of sense lines and to a second access line, wherein the second number of memory cells store a second number of elements and the second number of elements include the at least two element bit-lengths; and

a controller configured to control sensing circuitry to;

multiply each of the first number of elements by a corresponding element of the second number of elements by performing a number of operations comprising AND operations, OR operations and SHIFT operations without performing a sense line address access.

29. A method for performing multi-variable bit-length multiplication operations comprising:

performing a multi-variable bit-length multiplication operation in a memory array on;

a plurality (M) of first elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array, wherein at least two of the plurality of first elements have different bit-lengths; and

a plurality (M) of second elements stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array, wherein at least two of the plurality of second elements have different bit-lengths; and

providing a multiplication operation result that indicates a product of each element of the plurality of M first elements with a corresponding element of the plurality of M second elements.

30. The method of claim 29, wherein:

a first number of the M first elements and the M second elements are comprised of N bits and a second number of the M first elements and the M second elements are comprised of P bits; and

the first number of M first elements are multiplied by the corresponding first number of the M second elements and the second number of the M first elements are multiplied by the corresponding second number of the M second elements.

31. The method of claim 30, further comprising, identifying a most significant bit (MSB) for the M first elements and the M second elements.

32. The method of claim 31, further comprising, identifying a least significant bit (LSB) for each of the M first elements and the M second elements.

33. The method of claim 32, wherein performing the multiplication operation further comprises performing a number of iterations of operations using a vector mask element to isolate corresponding elements from the M first elements and the M second elements to indicate a number of bits of the M first elements and the M second elements, wherein the vector mask element indicates the most significant bit for the M first elements and the M second elements.

34. The method of claim 30, wherein a most-significant bit of a particular element of the plurality of first elements and a most-significant bit of a corresponding element of the plurality of second elements are stored in memory cells coupled to a same sense line.

35. The method of claim 34 wherein a least-significant bit of the particular element of the plurality of first elements and the corresponding element of the plurality of second elements are stored in a memory cell coupled to a same sense line.