APPARATUSES AND METHODS FOR STORING A DATA VALUE IN MULTIPLE COLUMNS

• US 20160064045A1
• Filed: 08/14/2015
• Published: 03/03/2016
• Est. Priority Date: 09/03/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: La Fratta, Patrick A.
• Granted Patent: US 9,847,110 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

Claims

1. An apparatus, comprising:

an array of memory cells coupled to sensing circuitry; and

a control component configured to cause;

computing of a data value equal to a logical OR between a digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array; and

storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector.

2. The apparatus of claim 1, wherein the control component is further configured to cause:

loading of the digit of the mask into an accumulator of the sensing circuitry; and

initially storing the data value equal to the logical OR in a sense amplifier of the sensing circuitry.

3. The apparatus of claim 1, wherein the control component is further configured to cause:

loading of the digit of the mask into a sense amplifier of the sensing circuitry; and

initially storing the data value equal to the logical OR in an accumulator of the sensing circuitry.

4. The apparatus of claim 1, wherein the control component is further configured to cause:

storing of the mask in a row, R, of the array; and

storing of the data value equal to the logical OR in the row of the array corresponding to an ith digit of the vector.

5. The apparatus of claim 1, wherein the control component is further configured to cause:

computing of a data value of an ith digit of the vector;

storing of the mask in row R of the array; and

storing of the data value equal to the logical OR in the R+ith row of the array corresponding to the ith digit of the vector.

6. The apparatus of claim 1, wherein the control component is further configured to cause:

computing of the data value equal to the logical OR between the digit of the mask and the data value stored in the memory cell only if the digit of the vector is a particular logical value; and

the data value equal to the logical OR to not be stored in the memory cell located in the column and R+ith row of the memory array if the digit of the vector is not the particular logical value.

7. The apparatus of claim 1, wherein the control component is further configured to cause setting of the data value stored in the memory cell located in the column and the row of the memory array corresponding to an ith digit of the vector to a logical value that does not make the logical OR true before the data value is computed to be equal to the logical OR.

8. The apparatus of claim 1, wherein the control component is configured to cause computing of the data value equal to the logical OR without transferring data values via an input/output (I/O) line outside the array and sensing circuitry.

9. The apparatus of claim 1, wherein the control component is configured to cause computing of the data value equal to the logical OR using transistors formed on pitch with transistors comprising the array.

10. An apparatus, comprising:

an array of memory cells coupled to sensing circuitry; and

a control component configured to cause;

computing of, for a plurality (i) of digits of a vector to be stored in one or more columns of the array, a data value equal to a logical function between;

a digit of a mask in the sensing circuitry; and

a data value stored in a memory cell located in a respective column and a row of the array corresponding to a digit of the vector to be stored in one or more columns of the array; and

storing of the data value equal to the logical function in the memory cell located in the column and the row of the array corresponding to the ith digit of the vector.

11. The apparatus of claim 10, wherein the control component is configured to cause loading of the digit of the mask corresponding to a respective column of the array into an accumulator of the sensing circuitry associated with the respective column.

12. The apparatus of claim 11, wherein the control component comprises a register configured to store the vector, and wherein the control component is configured to:

cause the sensing circuitry to compute the data value equal to the logical function whenever the digit of the vector stored in the register is a first logical value; and

not cause the sensing circuitry to compute the data value equal to the logical function whenever the digit of the vector stored in the register is a second logical value.

13. The apparatus of claim 12, wherein the control component is configured to cause setting of a data value stored in memory cells located in respective columns of the array to the second logical value prior to causing computing of the data value equal to the logical function.

14. The apparatus of claim 12, wherein the mask indicates those one or more columns of the array in which the vector is to be stored, and wherein the logical function is a logical OR operation.

15. The apparatus of claim 11, wherein the control component comprises a sequencer having a register, wherein:

the register is configured to store the vector; and

the sequencer is configured to;

cause the sensing circuitry to compute the data value equal to the logical OR whenever the ith digit of the vector stored in the register is a logical “

1”

; and

not cause the sensing circuitry to compute the data value equal to the logical OR whenever the ith digit of the vector stored in the register is a logical “

0.”

16. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array; and

a sequencer coupled to the sensing circuitry, the sequencer including;

a register configured to store a plurality of digits representing a numerical value;

a first output configured to select a row address of the array of memory cells; and

a second output configured to provide executable instructions to the sensing circuitry,

wherein the sequencer is configured to cause the sensing circuitry to store data values in multiple columns of memory cells of the array, the data values corresponding to the data values of the digits representing the numerical value.

17. The apparatus of claim 16, wherein the sequencer is configured to:

cause the sensing circuitry to perform a logical OR operation when a selected digit of the plurality of digits has a logic “

1”

value; and

not cause the sensing circuitry to perform a logical OR operation when the selected digit of the plurality of digits has a logic “

0”

value.

18. The apparatus of claim 16, wherein the sequencer is configured to select a next digit of the plurality of digits when a selected digit of the plurality of digits has a logic “

0”

value.

19. The apparatus of claim 16, wherein the sequencer is configured to increment the first output so as to correspond a respective selected digit of the plurality of digits with a different row in the array of memory cells.

20. A method for storing a data value in multiple columns, comprising:

loading a digit of a mask corresponding to a column of the memory array into an accumulator;

computing a data value equal to a logical OR between the digit of the mask in the accumulator and a data value stored in a memory cell located in the column and a row of the memory array corresponding to an ith digit of a vector to be stored in one or more columns of the memory array when the ith digit of the vector is a logical value that makes a logical OR true; and

storing the data value equal to the logical OR in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector.

21. The method of claim 20, further comprising storing the mask in a row of the memory array before loading the digit of the mask into the accumulator.

22. The method of claim 21, wherein:

storing the mask in the row of the memory array includes storing the mask in the Rth−

1 row of the memory array; and

the row of the memory array corresponding to the ith digit of the vector is the Rth+ith row.

23. The method of claim 22, wherein the row of the memory array corresponding to the least significant digit of the vector is the Rth row.

24. The method of claim 20, further comprising:

not computing the data value equal to the logical OR between the digit of the mask in the accumulator and the data value stored in the memory cell located in the column and the R+ith row of the memory array when the ith digit of the vector to be stored in one or more columns of the memory array is not the logical value that makes the logical OR true; and

not storing the data value equal to the logical OR in the memory cell located in the column and R+ith row of the memory array.

25. The method of claim 20, further comprising setting the data value stored in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector to a logical value that does not make the logical OR true before computing the data value equal to the logical OR.

26. The method of claim 20, further comprising clearing the data value stored in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector before computing the data value equal to the logical OR without clearing data values stored in memory cells located in columns in which the vector will not be stored.

27. The method of claim 20, further comprising

before computing the data value equal to the logical OR:

inverting the digit of the mask in the accumulator;

computing a data value equal to a logical AND between the inverted digit of the mask in the accumulator and the data value stored in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector to be stored in one or more columns of the memory array when the ith digit of the vector is the logical value that makes a logical OR true; and

storing the data value equal to the logical AND in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector.

28. The method of claim 20, further comprising

inverting the digit of the mask;

storing the inverted digit of the mask in one row of the memory array;

loading the inverted digit of the mask into the accumulator;

computing a data value equal to a logical AND between the inverted digit of the mask in the accumulator and the data value stored in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector to be stored in one or more columns of the memory array when the ith digit of the vector is the logical value that makes a logical OR true; and

storing the data value equal to the logical AND in the memory cell located in the column and the row of the memory array corresponding to the ith digit of the vector.

29. A method for storing a data value in multiple columns, comprising:

loading a digit of a mask corresponding to each of a respective column for a plurality of columns of the memory array into a sensing circuitry associated with the respective column;

setting data values in memory cells in multiple columns of the plurality of columns to a first logical value;

computing, in parallel for each of the respective columns of the plurality of columns, a data value equal to a logical function between the digit of the mask in the accumulator and a data value stored in a memory cell located in the respective column and a row of the memory array corresponding to an ith digit of a vector to be stored in the multiple columns of the plurality of columns when the ith digit of the vector is a second logical value different than the first logical value; and

storing the data value equal to the logical function in the memory cell located in the multiple columns and the row of the memory array corresponding to the ith digit of the vector.

30. The method of claim 29, wherein setting data values in memory cells in multiple columns of the plurality of columns to the first logical value does not include setting data values in memory cells in some of the plurality of columns to the first logical value.

31. The method of claim 29, wherein setting data values in memory cells in multiple columns of the plurality of columns to the first logical value includes setting data values in memory cells in those columns of the plurality of columns to which the vector is to be stored.

32. The method of claim 29, wherein computing and storing the data value equal to the logical function occurs for each digit of the vector for which the data value is not equal to the first logical value.

33. The method of claim 29, wherein computing and storing the data value equal to the logical function occurs for each digit of the vector for which the data value is equal to the second logical value.

34. The method of claim 29, wherein the digit of the mask corresponding to each of the multiple respective columns is a logical value that will cause the logical function to be different than the first logical value.

35. The method of claim 29, wherein the digit of the mask corresponding to each of the respective columns of the plurality of columns other than the multiple columns is a logical value that will not cause the logical function to be different than the data value stored in the memory cell located in the respective column and the row of the memory array corresponding to the ith digit of a vector.