COMPARISON OPERATIONS IN MEMORY

• US 20160064047A1
• Filed: 08/26/2015
• Published: 03/03/2016
• Est. Priority Date: 09/03/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tiwari, Sanjay
• Granted Patent: US 9,589,602 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders

Abstract

The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

Claims

1. An apparatus comprising:

a first group of memory cells coupled to a first access line and configured to store a plurality of first elements;

a second group of memory cells coupled to a second access line and configured to store a plurality of second elements; and

a controller configured to cause;

the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line; and

the plurality of first elements and the plurality of second elements to be compared in parallel.

2. The apparatus of claim 1, wherein the number of operations comprises a number of AND operations, OR operations, INVERT operations, and SHIFT operations.

3. The apparatus of claim 1, wherein the sensing circuitry comprises a number of transistors formed on pitch with the memory cells.

4. The apparatus of claim 3, wherein the sensing circuitry comprises a sense amplifier and a compute component.

5. The apparatus of claim 4, wherein the sensing circuitry comprises a sense amplifier comprising a primary latch and a compute component comprising a secondary latch.

6. A method for comparing elements comprising:

determining a respective bit length of each element of a plurality of first elements;

performing a plurality of comparison operations on;

the plurality of first elements stored in a first group of memory cells coupled to a first access line and to a number of sense lines of a memory array; and

a plurality of second elements stored in a second group of memory cells coupled to a second access line and to the number of sense lines of the memory array; and

providing an indication of whether a respective first element of the plurality of first elements is greater than a corresponding second element of the plurality of second elements.

7. The method of claim 6, wherein providing the indication further comprises proving an indication of whether each respective one of the plurality of first elements is greater than a corresponding respective one of the plurality of second elements.

8. The method of claim 6, further comprising performing the plurality of comparison operations in parallel.

9. The method of claim 8, wherein a number of operations used to perform the plurality of comparison operations in parallel is the same as a number of operations used to perform any one of the plurality of comparison operations.

10. The apparatus of claim 6, wherein each of the plurality of comparison operations is performed on a different element pair including corresponding elements from the plurality of first elements and the plurality of second elements.

11. The apparatus of claim 10, wherein elements in each of the different element pairs comprise vectors having a same length.

12. The apparatus of claim 11, wherein at least one of the plurality of first elements comprises a different quantity of bits than at least one other of the plurality of first elements.

13. An apparatus comprising:

a first group of memory cells coupled to a first access line and to a number of sense lines and configured to store a plurality of first elements;

a second group of memory cells coupled to a second access line and to the number of sense lines and configured to store a plurality of second elements;

a third group of memory cells configured to store results of a plurality of comparison operations performed on the first plurality of elements and the plurality of second elements, the third group of cells comprising;

a number of memory cells coupled to a third access line and to the number of sense lines; and

a number of memory cells coupled to a fourth access line and to the number of sense lines; and

a controller configured to control sensing circuitry to perform the plurality of comparison operations and store the results of the plurality of comparison operations in the third group of memory cells without transferring data via an input/output (I/O) line.

14. The apparatus of claim 13, wherein the controller is further configured to control the sensing circuitry to create a first destination bit-vector that identifies differences in the plurality of first elements as compared to the plurality of second elements.

15. The apparatus of claim 14, wherein the controller is further configured to control the sensing circuitry to create a second destination bit-vector that identifies differences in the plurality of second elements as compared to the plurality of first element.

16. The apparatus of claim 15, wherein the controller is further configured to control the sensing circuitry to replicate bits in the first destination bit-vector that identify differences in the plurality of first elements as compared to the plurality of second elements in a first replication phase.

17. The apparatus of claim 16, wherein the controller is further configured to control the sensing circuitry to replicate bits in the second destination bit-vector that identify differences in the plurality of second element as compared to the plurality of first elements in the first replication phase.

18. The apparatus of claim 17, wherein the controller is further configured to control the sensing circuitry to store in the first destination bit-vector differences in the first destination bit-vector as compared to the second destination bit-vector.

19. The apparatus of claim 18, wherein the controller is further configured to control the sensing circuitry to store in the second destination bit-vector differences in the second destination bit-vector as compared to the first destination bit-vector.

20. The apparatus of claim 19, wherein the controller is further configured to control the sensing circuitry to replicate bits in the first destination bit-vector in a second replication phase.

21. The apparatus of claim 20, wherein the controller is further configured to control the sensing circuitry to replicate bits in the second destination bit-vector in the second replication phase.

22. The apparatus of claim 21, wherein replicating bits in the first replication phase and the second replication phase includes performing a number of SHIFT operations.

23. The apparatus of claim 22, wherein the controller is further configured to control the sensing circuitry to store a static mask that defines a respective vector length for each of the plurality of first elements and for each of the plurality of second elements, and wherein the vector length of at least two of the plurality of first elements are different.

24. The apparatus of claim 23, wherein a quantity of the number of SHIFT operations performed is based on a particular vector length from the respective vector lengths of the plurality of first elements and the plurality of second elements.

25. The apparatus of claim 14, wherein the first destination bit-vector and the second destination bit-vector are the results of the plurality of comparison operations.