4-Switch Extended Commutation Cell

• US 20160064160A1
• Filed: 11/06/2015
• Published: 03/03/2016
• Est. Priority Date: 06/24/2014
• Status: Active Grant

• Current Assignee: Technische Universiteit Eindhoven
• Original Assignee: Technische Universiteit Eindhoven
• Inventors: Duarte, Jorge Luiz, Lemmen, Erik
• Granted Patent: US 9,917,515 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0095 Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4837 Flying capacitor converters

Abstract

The extended commutation cell (ECC) is a four-port, four-switch cell that allows for bidirectional energy transport in two orthogonal directions throughout the cell. By cascading multiple cells, a multilevel converter can be constructed with a high number of levels. The voltage across each cell capacitor can be adjusted independently of the load, resulting in high flexibility in output levels. Improved fault tolerance is also provided.

Claims

1. An extended commutation cell (ECC) subcircuit comprising:

4 ports (a, b, c, d);

a capacitor connected between ports c and d;

two internal nodes (N1, N2);

an inductor connected between N1 and N2;

a first switch configured to open or close an electrical connection between a and N1;

a second switch configured to open or close an electrical connection between c and N1;

a third switch configured to open or close an electrical connection between b and N2;

a fourth switch configured to open or close an electrical connection between d and N2.

2. The ECC subcircuit of claim 1, wherein the first switch, the second switch, the third switch and the fourth switch are individually selected from the group consisting of:

switches, transistors, metal-oxide-semiconductor field effect transistors, integrated gate-commutated thyristors, and insulated-gate bipolar transistors.

3. The ECC subcircuit of claim 1, wherein a first diode is connected in parallel to the first switch, a second diode is connected in parallel to the second switch, a third diode is connected in parallel to the third switch and a fourth diode is connected in parallel to the fourth switch.

4. The ECC subcircuit of claim 1, further comprising an output circuit to provide a single output from two ports of the ECC subcircuit.

5. An electrical power converter circuit comprising one or more ECC subcircuits as in claim 1 configured to provide multiple output voltage levels.

6. The electrical power converter circuit of claim 5, wherein the one or more ECC subcircuits are connected in cascade, wherein σ

is the number of the ECC subcircuits, whereby 2^c+1 output voltage levels can be provided.

7. The electrical power converter circuit of claim 5, further comprising an output circuit to provide a single output from two ports of one of the ECC subcircuits.

8. The electrical power converter circuit of claim 5, wherein the one or more ECC subcircuits are configured as a matrix with both cascaded connections and parallel connections between each column of the matrix, whereby improved fault tolerance is provided.

9. The electrical power converter circuit of claim 5, wherein the multiple output voltage levels are configured to synthesize an analog waveform by control of voltages on the capacitors of the ECC subcircuits.

10. The electrical power conversion circuit of claim 9, wherein the analog waveform is a sinusoid.

11. An ECC subcircuit comprising:

4 ports (a, b, c, d);

a capacitor connected between ports c and d;

three internal nodes (N1, N2, N3);

an inductor connected between N2 and N3;

a first switch configured to open or close an electrical connection between a and N1;

a second switch configured to open or close an electrical connection between c and N1;

a third switch configured to open or close an electrical connection between b and N2;

a fourth switch configured to open or close an electrical connection between d and N2;

a fifth switch configured to open an electrical connection between N1 and N3;

whereby improved fault tolerance is provided.

12. The ECC subcircuit of claim 11, wherein the first switch, the second switch, the third switch, the fourth switch and the fifth switch are individually selected from the group consisting of:

switches, transistors, metal-oxide-semiconductor field effect transistors, integrated gate-commutated thyristors, insulated-gate bipolar transistors, relays and fuses.

13. The ECC subcircuit of claim 11, wherein a first diode is connected in parallel to the first switch, a second diode is connected in parallel to the second switch, a third diode is connected in parallel to the third switch and a fourth diode is connected in parallel to the fourth switch.

14. The ECC subcircuit of claim 11, further comprising an output circuit to provide a single output from two ports of the ECC subcircuit.

15. An electrical power converter circuit comprising one or more ECC subcircuits as in claim 11 configured to provide multiple output voltage levels.

16. The electrical power converter circuit of claim 15, wherein the one or more ECC subcircuits are connected in cascade, wherein σ

is the number of the ECC subcircuits, whereby 2^c+1 output voltage levels can be provided.

17. The electrical power converter circuit of claim 15, further comprising an output circuit to provide a single output from two ports of one of the ECC subcircuits.

18. The electrical power converter circuit of claim 15, wherein the one or more ECC subcircuits are configured as a matrix with both cascaded connections and parallel connections between each column of the matrix, whereby improved fault tolerance is provided.

19. The electrical power converter circuit of claim 15, wherein the multiple output voltage levels are configured to synthesize an analog waveform by control of voltages on the capacitors of the ECC subcircuits.

20. The electrical power conversion circuit of claim 19, wherein the analog waveform is a sinusoid.