METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

• US 20160064224A1
• Filed: 08/27/2014
• Published: 03/03/2016
• Est. Priority Date: 08/27/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Yu-Hsiang, Fu, Ssu-I, Tsai, Shih-Hung, Jenq, Jyh-Shyang, Hsu, Chih-Kai
• Granted Patent: US 9,318,334 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region defined thereon; forming a plurality of fin-shaped structures on the substrate; forming a gate layer on the fin-shaped structures; forming a material layer on the gate layer; patterning the material layer for forming sacrificial mandrels on the gate layer in the first region; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; forming a patterned mask on the second region; and utilizing the patterned mask and the sidewall spacers to remove part of the gate layer.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first region and a second region defined thereon;

forming a plurality of fin-shaped structures on the substrate;

forming a gate layer on the fin-shaped structures;

forming a material layer on the gate layer;

patterning the material layer for forming sacrificial mandrels on the gate layer in the first region;

forming sidewall spacers adjacent to the sacrificial mandrels;

forming a dielectric layer on the sidewall spacers and the sacrificial mandrels;

planarizing the dielectric layer, the sidewall spacers, and the sacrificial mandrels so that the top surfaces of the sidewall spacers and the sacrificial mandrels are even with the top surface of the dielectric layer;

removing the sacrificial mandrels and the dielectric layer;

forming a patterned mask on the second region, wherein the patterned mask is not formed by sidewall image transfer (SIT) process; and

utilizing the patterned mask and the sidewall spacers to remove part of the gate layer until reaching the bottom of the gate layer.

2. The method of claim 1, wherein the gate layer comprises amorphous silicon or polysilicon.

3. The method of claim 1, wherein the material layer comprises amorphous silicon.

4. The method of claim 1, further comprising forming a silicon nitride layer and a silicon oxide layer on the gate layer before forming the material layer.

5. The method of claim 4, further comprising utilizing the sidewall spacers to remove part of the silicon nitride layer, part of the silicon oxide layer, and part of the gate layer.

6. The method of claim 1, further comprising trimming the sidewall spacers before forming the patterned mask.

7. The method of claim 1 further comprising trimming the sidewall spacers after forming the patterning mask.

8. The method of claim 1, further comprising performing a chemical mechanical polishing (CMP) process to planarize the gate layer before forming the material layer.

9. (canceled)