WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE

• US 20160064319A1
• Filed: 08/12/2015
• Published: 03/03/2016
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: SUZUKI, Tomohiro
• Granted Patent: US 9,406,599 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48106 the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/492 Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49866 characterised by the materials materials of the substrates H01L23/14, of the lead-frames H01L23/49579
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/15738 : the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H05K 2203/1572 : Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/10 : in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
• CPC Class Codes: H05K 3/108 : by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/4676 : Single layer compositions
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface. The pad includes the pad body, a first metal layer formed on an upper surface of the pad body and including an embedded part embedded in the insulating layer and a projecting part including upper and side surfaces and projecting from the upper surface of the insulating layer, and a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part. The upper surface of the pad body and the upper surface of the wiring pattern are on the same plane. The upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer.

Claims

1. A wiring substrate comprising:

an insulating layer including upper and lower surfaces;

a wiring layer including upper, lower, and side surfaces and being in a position that is recessed relative to the upper surface of the insulating layer;

a via wiring formed in the insulating layer and connected to the lower surface of the wiring layer; and

a solder resist layer formed on the upper surface of the insulating layer;

wherein the via wiring includes a first part contacting the lower surface of the wiring layer and a second part exposed from the lower surface of the insulating layer, the first part having an area smaller than an area of the second part,

wherein the wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface,

wherein the solder resist layer includes an upper surface and an opening that exposes the pad and a part of the upper surface of the insulating layer,

wherein the solder resist layer buries a step part formed by the upper surface of the insulating layer and the upper surface of the wiring pattern,

wherein the pad includes

the pad body including upper and lower surfaces, the lower surface of the pad body contacting the first part of the via wiring,

a first metal layer formed on the upper surface of the pad body, the first metal layer including an embedded part embedded in the insulating layer and a projecting part projecting from the upper surface of the insulating layer, the projecting part including upper and side surfaces of the first metal layer which is exposed from the upper surface of the insulating layer, and

a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part of the first metal layer,

wherein the upper surface of the pad body and the upper surface of the wiring pattern are on the same plane, and

wherein the upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer.

2. The wiring substrate as claimed in claim 1,

wherein the upper surface of the pad body is a smooth surface, and

wherein the upper surface of the wiring pattern is a roughened surface.

3. The wiring substrate as claimed in claim 1, wherein the upper surface of the insulating layer is a roughened surface.

4. The wiring substrate as claimed in claim 1, further comprising:

a second wiring layer formed on a side of the lower surface of the insulating layer; and

a second solder resist layer formed on the side of the lower surface of the insulating layer and including a second opening that selectively exposes the second wiring layer;

wherein the second wiring layer includes a lower outer edge part that is covered by the second solder resist layer,

wherein the second wiring layer includes a lower center part that is exposed in the second opening,

wherein the lower outer edge part of the second wiring layer has a roughness that is the same as a roughness of the upper surface of the wiring pattern, and

wherein the lower center part of the second wiring layer has a roughness that is the same as a roughness of the upper surface of the pad body.

5. The wiring substrate as claimed in claim 1, wherein the pad is configured to be connected to a bonding wire.

6. The wiring substrate as claimed in claim 1, wherein the pad body is formed of copper, the first metal layer is formed of nickel, and the second metal layer is formed of gold.

7. The wiring substrate as claimed in claim 1, wherein the insulating layer includes a reinforcement member.

8. A wiring substrate comprising:

an insulating layer including upper and lower surfaces;

a wiring layer including upper, lower, and side surfaces and being in a position that is recessed relative to the upper surface of the insulating layer;

a via wiring formed in the insulating layer and connected to the lower surface of the wiring layer; and

a solder resist layer formed on the upper surface of the insulating layer;

wherein the via wiring includes a first part contacting the lower surface of the wiring layer and a second part exposed from the lower surface of the insulating layer, the first part having an area smaller than an area of the second part,

wherein the wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface,

wherein the solder resist layer includes an upper surface and an opening that exposes the pad,

wherein the solder resist layer buries a step part formed by the upper surface of the insulating layer and the upper surface of the wiring pattern,

wherein the pad includes

the pad body including upper and lower surfaces, the lower surface of the pad body contacting the first part of the via wiring,

a first metal layer formed on the upper surface of the pad body, the first metal layer including an embedded part embedded in the insulating layer and a projecting part projecting from the upper surface of the insulating layer, the projecting part including upper and side surfaces of the first metal layer which is exposed from the upper surface of the insulating layer, and

a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part of the first metal layer,

wherein the upper surface of the pad body and the upper surface of the wiring pattern are on the same plane, and

wherein the upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer.

9. The wiring substrate as claimed in claim 8,

wherein the upper surface of the pad body is a smooth surface, and

wherein the upper surface of the wiring pattern is a roughened surface.

10. The wiring substrate as claimed in claim 8, wherein the upper surface of the insulating layer is a roughened surface.

11. The wiring substrate as claimed in claim 8, further comprising:

a second wiring layer formed on a side of the lower surface of the insulating layer; and

a second solder resist layer formed on the side of the lower surface of the insulating layer and including a second opening that selectively exposes the second wiring layer;

wherein the second wiring layer includes a lower outer edge part that is covered by the second solder resist layer,

wherein the second wiring layer includes a lower center part that is exposed in the second opening,

wherein the lower outer edge part of the second wiring layer has a roughness that is the same as a roughness of the upper surface of the wiring pattern, and

wherein the lower center part of the second wiring layer has a roughness that is the same as a roughness of the upper surface of the pad body.

12. The wiring substrate as claimed in claim 8, wherein the pad is configured to be connected to a bonding wire.

13. The wiring substrate as claimed in claim 8, wherein the pad body is formed of copper, the first metal layer is formed of nickel, and the second metal layer is formed of gold.

14. The wiring substrate as claimed in claim 8, wherein the insulating layer includes a reinforcement member.

15. A method for manufacturing a wiring substrate, the method comprising:

fabricating a support body having a metal foil including a thick foil and a thin foil that is thinner than the thick foil and peelably adhered to the thick foil, the metal foil being embedded in a resin layer to expose one surface of the thin foil;

forming a wiring layer on the one surface of the thin foil;

forming an insulating layer on the one surface of the thin foil to cover the wiring layer;

forming a via hole in the insulating layer that exposes a lower surface of the wiring layer that is on an opposite side of an upper surface of the wiring layer contacting the one surface of the thin foil;

forming a via wiring that fills the via hole to be connected to the lower surface of the wiring layer;

removing the thick foil and the resin layer, so that the thin foil remains on the insulating layer;

forming a step part by removing the thin foil with an etching process to expose the upper surface of the wiring layer contacting the one surface of the thin foil and further removing the upper surface of the wiring layer to expose the upper surface of the wiring layer in a position that is recessed relative to the upper surface of the insulating layer;

forming a solder resist layer on the upper surface of the insulating layer, the solder resist layer including an opening that exposes a part of the wiring layer corresponding to a pad body and covering another part of the wiring layer corresponding to a wiring pattern to bury the step part; and

fabricating a pad including

the pad body exposed in the opening of the solder resist layer,

a first metal layer formed on an upper surface of the pad body, the first metal layer including an embedded part embedded in the insulating layer and a projecting part projecting from the upper surface of the insulating layer, and

a second metal layer that covers upper and side surfaces of the projecting part of the first metal layer;

wherein the via wiring includes a first part contacting the lower surface of the wiring layer and a second part exposed from the lower surface of the insulating layer, the first part having an area smaller than an area of the second part,

wherein the upper surface of the pad body and the upper surface of the wiring pattern are on the same plane, and

wherein the upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer.

16. The method as claimed in claim 15,

wherein the one surface of the thin foil includes a roughened surface, and

wherein the removing of the thin foil includes transferring the roughened surface of the thin foil to the upper surface of the insulating layer.

17. The method as claimed in claim 15, further comprising:

roughening the upper surface of the pad body and the upper surface of the wiring pattern after the removing of the thin foil and before the forming of the solder resist layer; and

smoothening the upper surface of the pad body exposed in the opening after the forming of the solder resist layer.