SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20160064327A1
• Filed: 09/24/2014
• Published: 03/03/2016
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Ching-Ling, Huang, Chih-Sen, Hung, Ching-Wen, Wu, Jia-Rong, Chang, Tsung-Hung, Lee, Yi-Hui, Chen, Yi-Wei
• Granted Patent: US 9,466,521 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53261 Refractory-metal alloys
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate;

utilizing the first hard mask and the second hard mask as mask to remove part of the first ILD layer for forming a recess; and

forming a patterned metal layer in the recess, wherein the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.

2. The method of claim 1, further comprising:

forming a metal layer on the first hard mask, the second hard mask, and the first ILD layer;

forming a dielectric stack on the metal layer;

patterning the dielectric stack and the metal layer to form a patterned dielectric stack and the patterned metal layer in the recess;

forming a second ILD layer on the first hard mask, the second hard mask, the first ILD layer, the patterned dielectric stack and the patterned metal layer;

forming a first contact plug in the second ILD layer and the first ILD layer for electrically connecting to a source/drain region adjacent to the first metal gate; and

forming a second contact plug in the second ILD layer for electrically connecting to the patterned metal layer and forming a third contact plug in the second ILD layer for electrically connecting to the second metal gate.

3. The method of claim 2, wherein the step of patterning the dielectric stack and the metal layer comprises:

performing a first etching process to remove part of the dielectric stack for forming the patterned dielectric stack in the recess and on the first ILD layer; and

performing a second etching process to remove part of the metal layer.

4. The method of claim 2, wherein the step of patterning the dielectric stack and the metal layer comprises:

performing a first etching process to remove part of the dielectric stack for forming the patterned dielectric stack on the first ILD layer, the first hard mask, and the second hard mask; and

performing a second etching process to remove part of the metal layer.

5. The method of claim 2, wherein the dielectric stack comprises silicon nitride and silicon dioxide.

6. The method of claim 1, wherein the patterned metal layer comprises TiN.

7. A semiconductor device, comprising:

a substrate;

a first metal gate on the substrate;

a first hard mask on the first metal gate;

an interlayer dielectric (ILD) layer on top of and around the first metal gate; and

a patterned metal layer embedded in the ILD layer, wherein the top surface of the patterned metal layer is lower than the top surface of the first hard mask.

8. The semiconductor device of claim 7, further comprising a patterned dielectric stack on the patterned metal layer.

9. The semiconductor device of claim 8, wherein the patterned dielectric stack comprises silicon nitride and silicon dioxide.

10. The semiconductor device of claim 8, wherein the top surface of the patterned dielectric stack is lower than the top surface of the first hard mask.

11. The semiconductor device of claim 7, wherein the patterned metal layer comprises TiN.

12. The semiconductor device of claim 7, further comprising a first contact plug in the ILD layer and electrically connected to a source/drain region adjacent to the first metal gate.

13. The semiconductor device of claim 7, further comprising a second contact plug in the ILD layer and electrically connected to the patterned metal layer.

14. The semiconductor device of claim 7, further comprising:

a second metal gate on the substrate and adjacent to the first metal gate; and

a second hard mask on the second metal gate.

15. The semiconductor device of claim 14, further comprising a third contact plug in the ILD layer and electrically connected to the second metal gate.

16. The semiconductor device of claim 7, further comprising a shallow trench isolation (STI) in the substrate and directly under the patterned metal layer.

17. A semiconductor device, comprising:

a substrate;

a metal gate on the substrate;

a hard mask on the metal gate;

an interlayer dielectric (ILD) layer around the metal gate; and

a patterned metal layer embedded in the ILD layer, wherein the patterned metal layer comprises a step.

18. The semiconductor device of claim 17, further comprising a patterned dielectric stack on the patterned metal layer, wherein the patterned dielectric stack comprises silicon nitride and silicon dioxide.

19. The semiconductor device of claim 17, wherein the step is on part of the hard mask.

20. The semiconductor device of claim 17, wherein the patterned metal layer comprises TiN.