FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE WITH PROTECTION LAYER

• US 20160064377A1
• Filed: 08/29/2014
• Published: 03/03/2016
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Shiang-Bau
• Granted Patent: US 10,504,893 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate and an isolation structure formed on the substrate. The first fin structure is embedded in the isolation structure, and the first fin structure has an upper portion and a lower portion. The upper portion is above the isolation structure, and the lower portion is below the isolation structure. The FinFET device structure also includes a protection layer formed on the sidewalls of the lower portion of the first fin structure.

Claims

1. A fin field effect transistor (FinFET) device structure, comprising:

a first fin structure extending above a substrate;

an isolation structure formed on the substrate, wherein the first fin structure is embedded in the isolation structure, the first fin structure has an upper portion and a lower portion, the upper portion is above the isolation structure, and the lower portion is below the isolation structure; and

a protection layer formed on the sidewalls of the lower portion of the first fin structure, wherein the protection layer has a thickness selectable from any of the thicknesses included in a range from 0.5 nm to about 10 nm.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the protection layer comprises silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonnitride or combinations thereof.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the protection layer has a single layer or multiple layers.

5. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein a height ratio of the upper portion of the first fin structure to the lower portion of the first fin structure is in a range from 0.1 to about 0.5.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:

a second fin structure formed adjacent to the first fin structure, wherein the protection layer is extended from the sidewalls of the first fin structure to the sidewalls of the second fin structure.

7. The fin field effect transistor (FinFET) device structure as claimed in claim 6, wherein a pitch between the first fin structure and the second fin structure is in a range from 5 nm to about 1000 nm.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the fin structure has a width that gradually increases from the upper portion to the lower portion.

4. (canceled)

9. A fin field effect transistor (FinFET) device structure, comprising:

a substrate;

a first fin structure formed on the substrate, wherein the fin structure has a first sidewall and a second sidewall;

a second fin structure formed adjacent to the first fin structure, wherein the second fin structure has a third sidewall and a fourth sidewall, and wherein the third sidewall is adjoined to the second sidewall; and

a protection layer formed on a portion of the first fin structure and a portion of the second fin structure, wherein the protection layer is extended from the second sidewall to the third sidewall, wherein the protection layer has a thickness selectable from any of the thicknesses included in a range from 0.5 nm to about 10 nm.

10. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the first fin structure has an upper portion and a lower portion.

11. The fin field effect transistor (FinFET) device structure as claimed in claim 10, further comprising:

an isolation structure formed on the substrate, wherein the lower portion of the first fin structure is surrounded by the isolation structure.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 10, wherein a height ratio of the upper portion of the fin structure to the lower portion of the first fin structure is in a range from 0.1 to about 0.5.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the protection layer comprises silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonnitride or combinations thereof.

14. (canceled)

15-20. -20. (canceled)

21. A fin field effect transistor (FinFET) device structure, comprising:

a first fin structure extending above a substrate;

a second fin structure formed adjacent to the first fin structure;

an isolation structure formed on the substrate, wherein the first fin structure is embedded in the isolation structure, the first fin structure has an upper portion and a lower portion, the upper portion is above the isolation structure, and the lower portion is below the isolation structure; and

a protection layer formed on the sidewalls of the lower portion of the first fin structure, wherein the protection layer is extended from the sidewalls of the first fin structure to the sidewalls of the second fin structure,

wherein a pitch between the first fin structure and the second fin structure is selectable from any of the pitches in a range from 5 nm to about 1000 nm.

22. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein the protection layer comprises silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonnitride or combinations thereof.

23. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein the protection layer has a single layer or multiple layers.

24. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein the protection layer has a thickness selectable from any of a plurality of thicknesses in a range from 0.5 nm to about 10 nm.

25. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein a height ratio of the upper portion of the first fin structure to the lower portion of the first fin structure is in a range from 0.1 to about 0.5.

26. The fin field effect transistor (FinFET) device structure as claimed in claim 21, wherein the fin structure has a width that gradually increases from the upper portion to the lower portion.