Method to Control the Common Drain of a Pair of Control Gates and to Improve Inter-Layer Dielectric (ILD) Filling Between the Control Gates

• US 20160064401A1
• Filed: 08/26/2014
• Published: 03/03/2016
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Tsung-Hsueh, Wu, Chang-Ming, Liu, Shih-Chang, Min, Chung-Chiang
• Granted Patent: US 9,570,457 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. A semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.

Claims

1. A semiconductor structure for a split gate flash memory cell device, the semiconductor structure comprising:

a semiconductor substrate including a first source/drain region and a second source/drain region;

a control gate and a memory gate spaced over the semiconductor substrate between the first and second source/drain regions;

a charge trapping dielectric structure arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate; and

a hard mask arranged over the control gate and including an asymmetric profile, the asymmetric profile tapering in height away from the memory gate.

2. The semiconductor structure according to claim 1, wherein the asymmetric profile includes a first height at a first side proximate to the charge trapping dielectric structure, and a second height at a second side opposite the first side, wherein the second height is less than the first height.

3. The semiconductor structure according to claim 2, wherein the first height is about 45 nanometers, and wherein the second height is about 20 nanometers.

4. The semiconductor structure according to claim 1, further including:

a main sidewall structure arranged along sidewalls of the memory gate and the control gate;

a contact etch stop layer conformally arranged over the main sidewall structure, the charge trapping dielectric structure, the memory gate, and the hard mask; and

an inter-layer dielectric (ILD) layer arranged over and around the memory gate, the hard mask, the charge trapping dielectric structure, the control gate, the main sidewall structure, and the contact etch stop layer.

5. The semiconductor structure according to claim 1, wherein the semiconductor substrate includes a third source/drain region arranged on an opposite side of the second source/drain region as the first source/drain region, and wherein the semiconductor structure further includes:

a second control gate and a second memory gate spaced between the second and third source/drain regions;

a second charge trapping dielectric structure arranged between neighboring sidewalls of the second memory gate and the second control gate, and arranged under the second memory gate; and

a second hard mask arranged over the second control gate and including a second asymmetric profile, the second asymmetric profile tapering in height away from the second memory gate.

6. The semiconductor structure according to claim 5, wherein the control gate and the second control gate are arranged between the second source/drain region and corresponding ones of the memory gate and the second memory gate.

7. The semiconductor structure according to claim 5, wherein the asymmetric profile and the second asymmetric profile decrease in height towards the second source/drain region.

8. The semiconductor structure according to claim 5, further including:

an inter-layer dielectric (ILD) layer continuously filling a central region between the control gate and the second control gate, the central region including a ratio of height to width less than about one.

9. The semiconductor structure according to claim 8, wherein the height of the central region extends from about even with a top surface of the semiconductor substrate to a lowest point of a top surface of the hard mask, and wherein the width of the central region extends between sidewalls of the control gate and the second control gate.

10-19. -19. (canceled)

20. A semiconductor structure for a pair of split gate flash memory cell devices, the semiconductor structure comprising:

a semiconductor substrate including a first source/drain region, a second source/drain region, and a third source/drain region arranged on an opposite side of the second source/drain region as the first source/drain region;

first and second control gates and corresponding first and second memory gates spaced over the semiconductor substrate between the second source/drain region and corresponding ones of the first and third source/drain regions;

first and second charge trapping dielectric structures corresponding to the first and second memory gates and corresponding to the first and second control gates, wherein the first and second charge trapping dielectric structures are arranged between neighboring sidewalls of the corresponding memory gates and the corresponding controls gates, and wherein the first and second charge trapping dielectric structures are arranged under the corresponding memory gates; and

first and second hard masks arranged correspondingly over the first and second control gates and including an asymmetric profile, the asymmetric profile tapering in height towards the second source/drain region.

21. The semiconductor structure according to claim 20, wherein the asymmetric profile includes a first height proximate to the first and second charge trapping dielectric structures, and a second height proximate the second source/drain region, wherein the second height is less than the first height.

22. The semiconductor structure according to claim 20, further comprising:

a main sidewall structure arranged along sidewalls of the first and second memory gates and the first and second control gates;

a contact etch stop layer conformally arranged over the main sidewall structure, the first and second charge trapping dielectric structures, the first and second memory gates, and the first and second hard masks; and

an inter-layer dielectric (ILD) layer arranged over and around the first and second memory gates, the first and second hard masks, the first and second charge trapping dielectric structures, the first and second control gates, the main sidewall structure, and the contact etch stop layer.

23. The semiconductor structure according to claim 20, further comprising:

an inter-layer dielectric (ILD) layer continuously filling a central region between the first and second control gates, the central region including a ratio of height to width less than about one.

24. The semiconductor structure according to claim 23, wherein a height of the central region extends from about even with a top surface of the semiconductor substrate to top surfaces of the first and second hard masks, and wherein the width of the central region extends between sidewalls of the first and second control gates.

25. A split gate flash memory cell device comprising:

a pair of source/drain regions arranged in an upper side of a semiconductor substrate;

a control gate and a memory gate arranged over the semiconductor substrate and laterally spaced between the source/drain regions;

a charge trapping dielectric layer arranged between neighboring sidewalls of the control and memory gates, and arranged under the memory gate;

an asymmetric hard mask arranged over the control gate, wherein a height of the asymmetric hard mask decreases from a first sidewall that neighbors the memory gate to a second sidewall, opposite the first sidewall, that neighbor one of the source/drain regions; and

an interlayer dielectric (ILD) layer covering the control and memory gates and the asymmetric hard mask.

26. The split gate flash memory cell device according to claim 25, further comprising:

a main sidewall structure arranged along sidewalls of the control and memory gates; and

a contract etch stop layer lining the main sidewall structure, the memory gate, and the hard mask.

27. The split gate flash memory cell device according to claim 25, further comprising:

a second control gate arranged on an opposite side of one of the source/drain regions as the control gate; and

a second asymmetric hard mask arranged over the second control gate;

wherein a ratio of height to width of a region between the control gate and the second control gate is less than about one.

28. The split gate flash memory cell device according to claim 27, wherein the ILD layer continuously fills the region.

29. The split gate flash memory cell device according to claim 27, wherein a height of the second asymmetric hard mask tapers towards the one of the source/drain regions.

30. The split gate flash memory cell device according to claim 25, wherein the asymmetric hard mask and the control gate share a common footprint.