SEMICONDUCTOR AND OPTOELECTRONIC METHODS and DEVICES

• US 20160064439A1
• Filed: 11/09/2015
• Published: 03/03/2016
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C.
• Granted Patent: US 9,941,319 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14647 Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body

Abstract

A method for processing a semiconductor wafer, the method including: providing a semiconductor wafer including an image sensor pixels layer including a plurality of image sensor pixels, the layer overlaying a wafer substrate; and then bonding the semiconductor wafer to a carrier wafer; and then cutting off a substantial portion of the wafer substrate, and then processing the substantial portion of the wafer substrate for reuse.

Claims

1. A method for processing a semiconductor wafer, the method comprising:

providing a semiconductor wafer comprising an image sensor pixels layer comprising a plurality of image sensor pixels, said layer overlaying a wafer substrate; and

then

bonding said semiconductor wafer to a carrier wafer; and

then

cutting off a substantial portion of said wafer substrate, and then

processing said substantial portion of said wafer substrate for reuse.

2. A method according to claim 1, further comprising:

overlaying an oxide on top of said image sensor pixels layer; and

then

overlaying a mono-crystal layer on said oxide,

wherein said mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels.

3. A method according to claim 1, further comprising:

overlaying an oxide on top of said image sensor pixels layer; and

then

overlaying a mono-crystal layer on said oxide,

wherein said mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels, and

wherein said mono-crystal layer is less than 2 microns thick.

4. A method according to claim 1,

wherein said image sensor pixels layer comprises two crystalline layers, and

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer.

5. A method according to claim 1,

wherein said semiconductor wafer comprises two crystalline layers,

wherein said two crystalline layers comprise a first transistor layer and a second transistor layer.

6. A method according to claim 1,

wherein said image sensor pixels layer is less than 6 microns thick.

7. A method according to claim 1, further comprising:

overlaying an oxide on top of said image sensor pixels layer; and

then

overlaying a mono-crystal layer on said oxide,

wherein said mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels, and

wherein said single crystal transistors form a plurality of pixel control circuits.

8. An image sensor wafer, comprising:

a mono-crystallized silicon layer comprising a plurality of image sensor pixels, said mono-crystallized silicon layer bonded to a carrier wafer;

wherein said bonded leaves a re-useable base wafer used to hold said mono-crystallized silicon layer.

9. An image sensor wafer according to claim 8, further comprising:

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide,

wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels.

10. An image sensor wafer according to claim 8, further comprising:

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide,

wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels, and

wherein said second mono-crystal layer is less than 2 microns thick.

11. An image sensor wafer according to claim 8,

wherein said mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer.

12. An image sensor wafer according to claim 8,

wherein said mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first transistors layer and a second transistors layer.

13. An image sensor wafer according to claim 8,

wherein said mono-crystallized silicon layer is less than 6 microns thick.

14. An image sensor wafer according to 8, further comprising:

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide,

wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels,

wherein said single crystal transistors form a plurality of pixel control circuits.

15. An image sensor wafer, comprising:

a mono-crystallized silicon layer comprising a plurality of image sensor pixels, said mono-crystallized silicon layer bonded to a carrier wafer,

wherein said bonded leaves a re-useable base wafer used to hold said mono-crystallized silicon layer;

an oxide overlaying said mono-crystallized silicon layer; and

a second mono-crystal layer overlaying said oxide,

wherein said second mono-crystal layer comprises a plurality of single crystal transistors aligned to said image sensor pixels.

16. An image sensor wafer according to claim 15,

wherein said second mono-crystal layer is less than 2 microns thick.

17. An image sensor wafer according to claim 15,

wherein said mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first image sensor layer and a second image sensor layer.

18. An image sensor wafer according to claim 15,

wherein said mono-crystallized silicon layer comprises two crystalline layers,

wherein said two crystalline layers comprise a first transistors layer and a second transistors layer.

19. An image sensor wafer according to claim 15,

wherein said mono-crystallized silicon layer is less than 6 microns thick.

20. An image sensor wafer according to claim 15,

wherein said single crystal transistors form a plurality of pixel control circuits.