Semiconductor Device and a Method for Manufacturing a Semiconductor Device

• US 20160064477A1
• Filed: 08/27/2015
• Published: 03/03/2016
• Est. Priority Date: 08/28/2014
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver, Hirler, Franz, Siemieniec, Ralf, Yip, Li Juin
• Application Number:
  US14/837,223
• Publication Number:
  US 20160064477A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.

Claims

1. A semiconductor device comprising:

a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region;

a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the semiconductor substrate structure; and

an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.

2. The semiconductor device according to claim 1, wherein a field plate structure extends inside at least one trench and the field plate is insulated from the semiconductor substrate structure within the trench by an insulation layer.

3. The semiconductor device according to claim 1, wherein a field plate structure extends inside each trench of the plurality of needle-shaped cell trenches and the edge termination trench and the field plate structures are insulated from the semiconductor substrate structure within the trenches by an insulation layer, wherein the insulation layer within the plurality of needle-shaped cell trenches is thinner than the insulation layer within the edge termination trench.

4. The semiconductor device according to claim 1, wherein the trenches of the plurality of needle-shaped cell trenches are active needle-shaped cell trenches, each active needle-shaped cell trenches comprising a gate structure for controlling an adjacent channel of a field effect transistor structure.

5. The semiconductor device according to claim 1, wherein the needle-shaped trenches comprise a maximal lateral extension in one direction of less than 2 times a minimal lateral extension in another direction.

6. The semiconductor device according to claim 1, wherein the edge termination region comprises several closed strip-shaped edge termination trenches surrounding the cell region at the surface of the semiconductor substrate structure.

7. The semiconductor device according to claim 1, wherein a lateral distance between the outermost edge termination trench and an active needle-shaped cell trench closest to the outermost edge termination trench is larger than an extension of the outermost edge termination trench from the surface of the semiconductor substrate structure into the semiconductor substrate structure.

8. The semiconductor device according to claim 1, wherein the edge termination trench extends substantially as deep into the semiconductor substrate structure as the plurality of needle-shaped cell trenches.

9. The semiconductor device according to claim 1, wherein the edge termination trench comprises one of a rectangular, square, round, curved, hexagonal and octagonal layout.

10. The semiconductor device according to claim 1, wherein the edge termination trench extends mainly in parallel to edges of the semiconductor substrate structure and comprises diagonals or curvatures at corner regions of the semiconductor substrate structure.

11. The semiconductor device according to claim 1, wherein an inner layout line of the edge termination trench has a diagonal straight with an angle between 35°

and 55°

to a neighboring straight, whereas the diagonal straight faces a corner of the cell region.

12. The semiconductor device according to claim 1, wherein an inner layout line of the edge termination trench which faces the cell region is designed in a way that a distance from each point of the inner layout line to a nearest point of the outline of a nearest cell trench deviates by less than 20% from an average distance between the inner layout line of the edge termination trench and the nearest point of the outline of the nearest cell trench.

13. The semiconductor device according to claim 1, wherein a shape of the field plates within the plurality of needle-shaped cell trenches in a cross section parallel to the surface is substantially round, hexagonal, octagonal or square.

14. The semiconductor device according to claim 1, wherein the plurality of trenches is aligned in a rectangular, shifted or hexagonal grid.

15. Semiconductor device comprising:

a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region; and

a row of needle-shaped trenches within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure, wherein a plurality of field plate structures extend into the needle-shaped trenches of the row of needle-shaped trenches, wherein the field plate structures are insulated from the semiconductor substrate structure within the trenches by an insulating material structure extending throughout the row of needle-shaped trenches.

16. The semiconductor device according to claim 15, wherein a shortest lateral distance between an outer of two adjacent needle-shaped trenches is the same within the cell region as well as within the edge termination region, including a deviation of less than 10% in relation to the diameter of a trench.

17. The semiconductor device according to claim 15, wherein an insulation layer of the needle-shaped trenches of the edge termination region is thicker than the insulation layer of the needle-shaped trenches of the cell region.

18. The semiconductor device according to claim 15, wherein the row of needle-shaped trenches is merged.

19. A semiconductor device comprising:

a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region;

at least one cell trench within the cell region reaching from a surface of the semiconductor substrate structure into the semiconductor substrate structure;

at least one edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure; and

an insulation layer within the trenches,

wherein the insulation layer within the at least one cell trench is thinner than the insulation layer within the at least one edge termination trench.

20. The semiconductor device according to claim 19, wherein a field plate structures extend inside at least an inner edge termination trench and an outermost edge termination trench and the field plates are insulated from the semiconductor substrate structure by insulation layers within the edge termination trenches;

and

a thickness of the field plate structures decreases from the inner to the outermost edge termination trench.