MONOLITHIC THREE DIMENSIONAL NAND STRINGS AND METHODS OF FABRICATION THEREOF

• US 20160064532A1
• Filed: 08/26/2014
• Published: 03/03/2016
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: MAKALA, Raghuveer S., ZHANG, Yanli, SHARANGPANI, Rahul, LEE, Yao-Sheng, MATAMIS, George, ALSMEIER, Johann, KANAKAMEDALA, Senaka Krishna
• Granted Patent: US 9,691,884 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.

Claims

1. A monolithic three dimensional NAND string, comprising:

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;

a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein each control gate electrode comprises a top surface, a bottom surface opposite the top surface and a first side surface facing the at least one end portion of the semiconductor channel, and the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

an insulating material layer extending substantially parallel to the major surface of the substrate and between the first control gate electrode located in the first device level and the second control gate electrode located in the second device level, wherein the insulating material layer comprises a first insulating material portion located adjacent to a bottom surface of the first control gate electrode, a second insulating material portion located adjacent to a top surface of the second control gate electrode, and third insulating material portion located between the first insulating material portion and the second insulating material portion, wherein the third insulating material portion comprises a material having a dielectric constant that is lower than a dielectric constant of a material of the first insulating material portion and a dielectric constant of a material of the second insulating material portion;

at least one charge storage region extending substantially perpendicular to the major surface of the substrate and located adjacent to at least the first side surfaces of each of the control gate electrodes;

a blocking dielectric located adjacent to at least the first side surfaces of each of the control gate electrodes and located between the charge storage region and each of the control gate electrodes; and

a tunnel dielectric located between the charge storage region and the semiconductor channel.

2. The monolithic three dimensional NAND string of claim 1, wherein the first and second insulating material portions comprise the same insulating material, and the third insulating portion comprises an insulating material having a dielectric constant below 3.9.

3. The monolithic three dimensional NAND string of claim 2, wherein the first and second insulating portions comprise silicon oxide formed using a tetraethyl orthosilicate (TEOS) source and the third insulating portion comprises silicon oxide that is doped to provide a dielectric constant lower than the dielectric constant of the silicon oxide of the first and second insulating portions.

4. The monolithic three dimensional NAND string of claim 3, wherein the silicon oxide of the third insulating portion is doped with at least one of fluorine and carbon.

5. The monolithic three dimensional NAND string of claim 4, wherein the blocking dielectric surrounds each of the control gate electrodes over the top, bottom and first side surfaces of control gate electrodes, and the insulating material layer is separated from the adjacent control gate electrodes by the blocking dielectric.

6. The monolithic three dimensional NAND string of claim 5, wherein the insulating layer comprises a first insulating layer, and the NAND string further comprises a plurality of vertically spaced apart second insulating layer segments that extend substantially perpendicular to the major surface of the substrate, the second insulating layer segments are different than the blocking dielectric and located between respective portions of the blocking dielectric that extend adjacent to the first side surfaces of the respective control gate electrodes.

7. The monolithic three dimensional NAND string of claim 5, wherein the insulating layer comprises a first side surface facing the at least one end portion of the semiconductor channel, and a second side surface opposite the first side surface, and the blocking dielectric extends over the second side surface of the insulating layer.

8. The monolithic three dimensional NAND string of claim 1, wherein the at least one charge storage region comprises a continuous dielectric charge trap layer that extends substantially perpendicular to the major surface of the substrate adjacent to the blocking dielectric and each of the control gate electrodes.

9. The monolithic three dimensional NAND string of claim 8, wherein the at least one charge storage region comprises a plurality of spaced apart floating gates.

10. The monolithic three dimensional NAND string of claim 1, wherein the blocking dielectric comprises a stack of at least two different insulating layers.

11. The monolithic three dimensional NAND string of claim 10, wherein the at least two different insulating layers are selected from a group consisting of a metal oxide, silicon oxide and silicon nitride or combinations thereof.

12. The monolithic three dimensional NAND string of claim 11, wherein the metal oxide comprises at least one of aluminum oxide and hafnium oxide.

13. The monolithic three dimensional NAND string of claim 1, further comprising one of a source or drain electrode which contacts the semiconductor channel from above the device levels, and another one of a source or drain electrode which contacts the semiconductor channel below the device levels to form the monolithic three dimensional NAND string.

14. The monolithic three dimensional NAND string of claim 1, wherein:

the semiconductor channel has a U-shaped side cross section;

two wing portions of the U-shaped semiconductor channel extend substantially perpendicular to a major surface of the substrate are connected by a connecting portion which extends substantially parallel to the major surface of the substrate;

one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above; and

another one of a source or drain electrode contacts the second wing portion of the semiconductor channel from above.

15. The monolithic three dimensional NAND string of claim 1, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in monolithic, three dimensional array of NAND strings;

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and

the silicon substrate contains located thereon an integrated circuit comprising a driver circuit for the array of NAND strings.

16. A monolithic three dimensional NAND string, comprising:

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;

a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein each control gate electrode comprises a top surface, a bottom surface opposite the top surface and a first side surface facing the at least one end portion of the semiconductor channel, and the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

a plurality of first insulating material layers extending substantially parallel to the major surface of the substrate between the respective device levels, wherein each of the plurality of first insulating material layers is adjacent to a bottom surface of a respective one of the plurality of control gate electrodes;

a plurality of second insulating material layers extending substantially parallel to the major surface of the substrate between the respective device levels, wherein each of the plurality of second insulating material layers is adjacent to a top surface of a respective one of the plurality of control gate electrodes;

a plurality of air gaps between the respective device levels, wherein each air gap comprises a void region enclosed on a top side by a first insulating material layer and on a bottom side by a second insulating material layer, and at least a first portion of the air gap facing the semiconductor channel has a substantially rectangular-shaped cross-section in a plane extending perpendicular to the major surface of the substrate;

at least one charge storage region extending substantially perpendicular to the major surface of the substrate and located adjacent to at least the first side surfaces of each of the control gate electrodes;

a blocking dielectric located adjacent to at least the first side surfaces of each of the control gate electrodes and located between the charge storage region and each of the control gate electrodes; and

a tunnel dielectric located between the charge storage region and the semiconductor channel.

17. The monolithic three dimensional NAND string of claim 16, wherein the first and second insulating material layers comprise the same insulating material.

18. The monolithic three dimensional NAND string of claim 17, wherein the first and second insulating material layers comprise silicon oxide formed using a tetraethyl orthosilicate (TEOS) source.

19. The monolithic three dimensional NAND string of claim 16, further comprising:

a plurality of vertically spaced apart third insulating layer segments that extend substantially perpendicular to the major surface of the substrate, the third insulating layer segments being located between respective portions of the blocking dielectric that extend adjacent to the first side surfaces of the respective control gate electrodes.

20. The monolithic three dimensional NAND string of claim 19, wherein each of the air gaps is enclosed on a first side of the air gap facing the semiconductor channel by a respective one of the plurality of the vertically separated third insulating layer segments.

21. The monolithic three dimensional NAND string of claim 16, further comprising a high-etch rate insulating material having a higher etch rate than the material of the first insulating layer and the second insulating layer when exposed to the same etching medium, the high-etch rate insulating material located between the respective device levels and each of the air gaps is enclosed on the first side of the air gap facing the semiconductor channel by the high etch rate insulating material.

22. The monolithic three dimensional NAND string of claim 21, wherein the first insulating layer, the second insulating layer and the high-etch rate insulating material comprise silicon oxide.

23. The monolithic three dimensional NAND string of claim 22, wherein the high-etch rate insulating material comprises silicon oxide that is doped with at least one of boron and phosphorus.

24. The monolithic three dimensional NAND string of claim 22, wherein the high-etch rate insulating material comprises silicon oxide that is deposited by CVD using a dichlorosilane (H₂SiCl₂) source, and the first insulating layer and the second insulating layer comprise silicon oxide that is deposited by CVD using a disilane (Si₂H₆) source.

25. The monolithic three dimensional NAND string of claim 22, wherein the high-etch rate insulating material comprises silicon oxide that is deposited by High Aspect Ratio Process (HARP) non-plasma based CVD using TEOS and ozone sources and the first insulating layer and the second insulating layer comprise silicon oxide that is deposited by high density plasma (HDP) CVD.

26. The monolithic three dimensional NAND string of claim 22, wherein the high-etch rate insulating material comprises silicon oxide borosilicate glass or borophosphosilicate glass, and the first insulating layer and the second insulating layer comprise silicon oxide that is deposited using a TEOS source.

27. The monolithic three dimensional NAND string of claim 22, further comprising a plurality of vertically spaced apart third insulating layer segments that extend substantially perpendicular to the major surface of the substrate, the third insulating layer segments being located between respective portions of the blocking dielectric that extend adjacent to the first side surfaces of the respective control gate electrodes and the third insulating layer segments being located adjacent to the high-etch rate insulating material opposite the air gaps.

28. The monolithic three dimensional NAND string of claim 16, wherein each of the air gaps is enclosed on a second side of the air gap opposite the semiconductor channel by an insulating material.

29. The monolithic three dimensional NAND string of claim 28, wherein the insulating material defines a substantially concave second side surface of the air gap.

30. The monolithic three dimensional NAND string of claim 16, wherein the at least one charge storage region comprises a continuous dielectric charge trap layer that extends substantially perpendicular to the major surface of the substrate adjacent to the blocking dielectric and each of the control gate electrodes.

31. The monolithic three dimensional NAND string of claim 30, wherein the at least one charge storage region comprises a plurality of spaced apart floating gates

32. The monolithic three dimensional NAND string of claim 16, wherein the blocking dielectric comprises a stack of at least two different insulating layers.

33. The monolithic three dimensional NAND string of claim 32, wherein the at least two different insulating layers are selected from a group consisting of a metal oxide, silicon oxide and silicon nitride or combinations there of.

34. The monolithic three dimensional NAND string of claim 33, wherein the metal oxide comprises at least one of aluminum oxide and hafnium oxide.

35. The monolithic three dimensional NAND string of claim 16, further comprising one of a source or drain electrode which contacts the semiconductor channel from above the device levels, and another one of a source or drain electrode which contacts the semiconductor channel below the device levels to form the monolithic three dimensional NAND string.

36. The monolithic three dimensional NAND string of claim 16, wherein:

the semiconductor channel has a U-shaped side cross section;

two wing portions of the U-shaped semiconductor channel extend substantially perpendicular to a major surface of the substrate are connected by a connecting portion which extends substantially parallel to the major surface of the substrate;

one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above; and

another one of a source or drain electrode contacts the second wing portion of the semiconductor channel from above.

37. The monolithic three dimensional NAND string of claim 16, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in monolithic, three dimensional array of NAND strings;

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and

the silicon substrate contains located thereon an integrated circuit comprising a driver circuit for the array of NAND strings.

38. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating first material layers and second material layers over a major surface of a substrate, wherein each of the second material layers comprises a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, and the first material layers comprise a material that is different than the first silicon oxide material and the second silicon oxide material;

etching the stack to form a front side opening in the stack;

forming at least a portion of a memory film over a sidewall of the front side opening; and

forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening,

wherein at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.

39. The method of claim 38, wherein the first silicon oxide material has a lower dielectric constant than the dielectric constant of the second silicon oxide material.

40. The method of claim 39, wherein the first silicon oxide material comprises the material which has the dielectric constant below 3.9.

41. The method of claim 39, wherein the layers of the second silicon oxide material are formed by plasma enhanced chemical vapor deposition (PECVD) using a tetraethyl orthosilicate (TEOS) source, and the first silicon oxide material is doped to provide a dielectric constant lower than the dielectric constant of the second silicon oxide material.

42. The method of claim 41, wherein the first silicon oxide material is doped with at least one of fluorine and carbon.

43. The method of claim 38, further comprising:

etching through the stack to form a back side opening in the stack;

removing by etching at least a portion of the first material layers through the back side opening to form back side recesses between the second material layers;

forming a blocking dielectric in the back side recesses through the back side opening; and

forming control gates over the blocking dielectric in the back side recesses through the back side opening.

44. The method of claim 43, wherein the blocking dielectric is formed in the back side recesses and over a sidewall of the back side opening in the stack, and the blocking dielectric surrounds the respective second material layers on three sides of the second material layers.

45. The method of claim 38, wherein the first silicon oxide material has a higher etch rate than the second silicon oxide material when exposed to the same etching medium, the method further comprising:

etching through the stack to form a back side opening in the stack; and

removing by etching at least a portion of the first silicon oxide material through the back side opening to form back side recesses between the two layers of the second silicon oxide material.

46. The method of claim 45, further comprising:

forming an insulating material over a sidewall of the back side opening to enclose the back side recesses and form the air gap in between each respective two layers of the second silicon oxide material.

47. The method of claim 45, further comprising:

forming a cover layer of an insulating material over the sidewall of the front side opening in the stack, wherein the at least one memory film is formed over the cover layer, and the first silicon oxide material is etched through the back side opening to remove all of the first silicon oxide material from the back side recesses, stopping the etch at the cover layer.

48. The method of claim 45, wherein only a portion of the first silicon oxide material is removed, and the air gap is enclosed on a side of the air gap facing the semiconductor channel by a portion of the first silicon oxide material that is not removed by etching.

49. The method of claim 45, further comprising:

removing by etching at least a portion of the first material layers through the back side opening to form second back side recesses between the second material layers;

forming a blocking dielectric in the second back side recesses through the back side opening; and

forming control gates over the blocking dielectric in the second back side recesses through the back side opening.

50. The method of claim 45, further comprising:

forming a third silicon oxide material in the back side recesses through the back side opening, wherein the third silicon oxide material has a lower dielectric constant than the dielectric constant of the second silicon oxide material.

51. The method of claim 50, wherein the third silicon oxide material comprises the material which has a dielectric constant below 3.9.

52. The method of claim 50, wherein the layers of the second silicon oxide material are formed by chemical vapor deposition (CVD) using a tetraethyl orthosilicate (TEOS) source, and the third silicon oxide material comprises silicon oxide that is doped to provide a dielectric constant lower than the dielectric constant of the second silicon oxide material.

53. The method of claim 52, wherein the third silicon oxide material is doped with at least one of fluorine and carbon.

54. The method of claim 45, wherein first silicon oxide material is doped with at least one of boron and phosphorus.

55. The method of claim 45, wherein the first silicon oxide material is deposited by CVD using a dichlorosilane (H₂SiCl₂) source, and the second silicon oxide material is deposited by CVD using a disilane (Si₂H₆) source.

56. The method of claim 45, wherein the first silicon oxide material is deposited by High Aspect Ratio Process (HARP) non-plasma based CVD using TEOS and ozone sources and the second silicon oxide material is deposited by high density plasma (HDP) CVD.

57. The method of claim 45, wherein the first silicon oxide material comprises borosilicate glass or borophosphosilicate glass, and the second silicon oxide material is deposited using a TEOS source.

58. The method of claim 38, wherein the memory film comprises at least one charge storage region and a tunnel dielectric extending over the sidewall of the front side opening, wherein the tunnel dielectric is located between the at least one charge storage region and the semiconductor channel.

59. The method of claim 38, further comprising forming one of a source or drain electrode which contacts the semiconductor channel from above, and another one of a source or drain electrode which contacts the semiconductor channel below the stack to form the monolithic three dimensional NAND string.

60. The method of claim 38, wherein:

the semiconductor channel has a U-shaped side cross section;

two wing portions of the U-shaped semiconductor channel extend substantially perpendicular to a major surface of the substrate are connected by a connecting portion which extends substantially parallel to the major surface of the substrate;

one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above; and

another one of a source or drain electrode contacts the second wing portion of the semiconductor channel from above.