VERTICAL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
First Claim
1. A vertical transistor, comprising:
- a source-channel-drain structure comprising a source, a drain over the source and a channel between the source and the drain;
a gate surrounding a portion of the channel, the gate being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate being configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor; and
a gate dielectric layer between the channel and the gate.
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Accused Products
Abstract
A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.
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Citations
20 Claims
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1. A vertical transistor, comprising:
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a source-channel-drain structure comprising a source, a drain over the source and a channel between the source and the drain; a gate surrounding a portion of the channel, the gate being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate being configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor; and a gate dielectric layer between the channel and the gate. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A vertical transistor, comprising:
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a source-channel-drain structure comprising a source, a drain over the source and a channel between the source and the drain; a gate surrounding a portion of the channel; a gate dielectric layer between the channel and the gate; and an ILD over the gate and in contact with the gate dielectric layer and surrounding another portion of the channel, the ILD being configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the ILD being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A method of manufacturing a vertical transistor, comprising:
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forming a source-channel-drain structure, wherein the source-channel-drain structure comprises a source, a drain over the source and a channel between the source and the drain; forming a gate dielectric layer surrounding the channel; forming a gate surrounding a portion of the gate dielectric layer; and forming an ILD over the gate and surrounding and in contact with another portion of the gate dielectric layer, wherein the gate and the ILD are configured to independently or collectively provide strain substantially along an extending direction of the channel. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification