Semiconductor Device with a Termination Mesa Between a Termination Structure and a Cell Field of Field Electrode Structures

• US 20160064548A1
• Filed: 08/27/2015
• Published: 03/03/2016
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Laforet, David, Siemieniec, Ralf
• Granted Patent: US 9,972,714 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a cell field with a plurality of field electrode structures and cell mesas. The field electrode structures are arranged in lines. The cell mesas separate neighboring ones of the field electrode structures from each other. Each field electrode structure includes a field electrode and a field dielectric separating the field electrode from a semiconductor body. A termination structure surrounds the cell field, extends from a first surface into the semiconductor body, and includes a termination electrode and a termination dielectric separating the termination electrode from the semiconductor body. The termination and field dielectrics have the same thickness. A termination mesa, which is wider than the cell mesas, separates the termination structure from the cell field.

Claims

1. A semiconductor device, comprising:

a cell field comprising a plurality of field electrode structures arranged in lines and cell mesas separating neighboring ones of the field electrode structures from each other, wherein each field electrode structure comprises a field electrode and a field dielectric separating the field electrode from a semiconductor body;

a termination structure surrounding the cell field, extending from a first surface into the semiconductor body, and comprising a termination electrode a termination dielectric separating the termination electrode from the semiconductor body, the termination and field dielectrics having a same thickness; and

a termination mesa wider than the cell mesas and separating the termination structure from the cell field.

2. The semiconductor device of claim 1, wherein

a mean dopant concentration in the termination mesa is lower than a mean dopant concentration in a second drift zone section in the cell mesas, the second drift zone section directly adjoining a first drift zone section formed in a contiguous section of the semiconductor body between the field electrode structures and a second surface opposite to the first surface.

3. The semiconductor device of claim 1, further comprising:

a gate structure surrounding the field electrode structures, the gate structure comprising a gate electrode and a gate dielectric separating the gate electrode from the semiconductor body.

4. The semiconductor device of claim 3, wherein

portions of the cell mesas are formed between the gate structure and the field electrode structures, respectively.

5. The semiconductor device of claim 4, wherein

the gate structure forms a grid embedding transistor sections of a plurality of transistor cells, each transistor cell assigned to a field electrode structure.

6. The semiconductor device of claim 1, wherein

a width of the field electrode structures is equal to a width of the termination structure.

7. The semiconductor device of claim 1, wherein

a width of the termination mesa is uniform along straight sections of the termination mesa.

8. The semiconductor device of claim 1, wherein

a width of the termination mesa is uniform along beveled portions between orthogonal straight sections of the termination mesa.

9. The semiconductor device of claim 1, wherein

a distance between the termination structure and the cell field is uniform.

10. The semiconductor device of claim 1, wherein

the field electrode structures are arranged matrix-like in lines and rows orthogonal to the lines, and the termination mesa comprises at least four straight sections along four sides of a rectangular cell field.

11. The semiconductor device of claim 10, wherein

the termination mesa comprises slanted sections connecting two orthogonal straight sections, respectively.

12. The semiconductor device of claim 1, wherein

the field electrode structures are arranged in shifted lines, and the termination mesa comprises straight sections parallel to the shifted lines and zigzag sections orthogonal to the shifted lines.

13. The semiconductor device of claim 12, wherein

the zigzag sections of the termination mesa comprise bulges in the longitudinal projection of indented lines of field electrode structures.

14. The semiconductor device of claim 12, wherein

the zigzag sections have uniform width.

15. An electronic assembly, comprising:

a semiconductor device that comprises a cell field comprising a plurality of field electrode structures arranged in lines and cell mesas separating neighboring ones of the field electrode structures from each other, wherein each field electrode structure comprises a field electrode and a field dielectric separating the field electrode from a semiconductor body;

a termination structure surrounding the cell field, extending from a first surface into the semiconductor body, and comprising a termination electrode and a termination dielectric separating the termination electrode from the semiconductor body, the termination and field dielectrics having a same thickness; and

a termination mesa wider than the cell mesas and separating the termination structure from the cell field.

16. A method of manufacturing a semiconductor device, the method comprising:

forming, in a cell field of a semiconductor layer that contains dopants, field electrode trenches arranged in lines and separated by cell mesas formed from portions of the semiconductor layer;

forming, in the semiconductor layer a termination trench surrounding the cell field, wherein a portion of the semiconductor layer between the cell field and the termination trench forms a termination mesa, which is wider than the cell mesas; and

forming, by thermal oxidation, a field oxide layer equably lining the field electrode and termination trenches.

17. The method of claim 16, wherein

dopants contained in oxidizing portions of the semiconductor layer segregate and contribute to final dopant concentrations in the cell mesas and the termination mesa, and a dopant concentration difference between a first mean dopant concentration in the cell mesas and a second mean dopant concentration in the termination mesa is proportional to a ratio of a total volume of the cell mesas to a total volume of the termination mesa.

18. The method of claim 16, further comprising:

forming and removing, before forming the field oxide layer, a sacrificial oxide layer lining the field electrode and termination trenches.

19. The method of claim 16, wherein

the field electrode trenches and the termination trench are formed contemporaneously.

20. The method of claim 16, further comprising

depositing a field dielectric layer on the field oxide layer.