POWER MANAGEMENT INTEGRATED CIRCUIT, POWER MANAGEMENT METHOD, MOBILE DEVICE AND CLOCK ADJUSTING METHOD

• US 20160066280A1
• Filed: 07/07/2015
• Published: 03/03/2016
• Est. Priority Date: 08/26/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Dongsuk Shin, Youngduk Kim
• Inventors: HEO, JUNGHUN, KIM, YOUNGDUK, KIM, JOONSEOK, SHIN, DONGSUK
• Granted Patent: US 10,383,062 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: H04W 52/0261 managing power supply demand, e.g. depending on battery level
• CPC Class Codes: H04W 52/0287 changing the clock frequency of a controller in the equipment
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed.

Claims

1. A power management method for a mobile device including a battery providing a power supply voltage, the method comprising:

generating a negative alarm signal when the power supply voltage is higher than a reference voltage, and generating a positive alarm signal when the power supply voltage is lower than the reference voltage;

providing one of the negative alarm signal and the positive alarm signal to a System-on-Chip (SoC) including a Central Processing Unit (CPU) that operates in response to an operating clock,

wherein the operating clock has a first frequency in response to the negative alarm signal and a second frequency lower than the first frequency in response to the positive alarm signal.

2. The power management method of claim 1, further comprising:

generating the operating clock by dividing a source clock received by the SoC using a clock division ratio.

6. The power management method of claim 1, wherein the providing of the one of the negative alarm signal and the positive alarm signal to the SoC comprises:

receiving the power supply voltage in a power management integrated circuit (PMIC), separate from the SoC, and comparing the power supply voltage to the reference voltage to generate the one of the negative alarm signal and the positive alarm signal.

10. The power management method of claim 1, wherein the SoC further includes an interrupt controller that generates an interrupt signal that controls the CPU in responsive to the received one of the negative alarm signal and the positive alarm signal.

3-5. -5. (canceled)

7-9. -9. (canceled)

11-24. -24. (canceled)

25. A mobile device comprising:

a power management circuit that receives a power supply voltage and compares the power supply voltage to a reference voltage, wherein the power management circuit generates a negative alarm signal when the power supply voltage is higher than a reference voltage and generates a positive alarm signal when the power supply voltage is lower than the reference voltage;

a System-on-Chip (SoC) that receives one of the negative alarm signal and the positive alarm signal, and comprises;

a Central Processing Unit (CPU) that operates in response to an operating clock; and

a clock divider that generates the operating clock, wherein the operating clock is generated with a first frequency in response to the negative alarm signal and a second frequency lower than the first frequency in response to the positive alarm signal.

26. The mobile device of claim 25, wherein the clock divider generates the operating clock by dividing a source clock received by the SoC using a clock division ratio.

27. The mobile device of claim 26, wherein the clock divider generates the operating clock by either dividing the source clock using a first clock division ratio in response to the negative alarm signal, or dividing the source clock using a second clock division ratio, different from the first clock division ratio in response to the positive alarm signal.

28. The mobile device of claim 27, wherein the SoC comprises a register storing clock division information defining the first clock division ratio and the second clock division ratio.

29. The mobile device of claim 25, wherein the power management circuit is provided in a power management integrated circuit (PMIC) separate from the SoC, the PMIC comprising:

a reference voltage generator that generates the reference voltage; and

a comparator that compares the power supply voltage and the reference voltage to generate at least one of the negative alarm signal and the positive alarm signal.

30. The mobile device of claim 29, wherein the PMIC further comprises:

a register storing power management information, wherein the reference voltage generator generates the reference voltage in response to the power management information.

31. The mobile device of claim 25, wherein the power management circuit is integrated in the SoC.

32-36. -36. (canceled)

37. A mobile device, comprising:

a battery providing a power supply voltage;

a power management integrated circuit (PMIC) that compares the power supply voltage with a reference voltage to provide a comparison signal, and generates an alarm signal from the comparison signal;

a System-on-Chip (SoC) including a Central Processing Unit (CPU) that operates in response to an operating clock, a clock divider that generates the operating clock in response to the alarm signal, and a current control unit that generates clock division information and power management information,

wherein the power management information is communicated from the SoC to the PMIC via an interface connection, and the PMIC generates the comparison signal in response to the power management information.

38. The mobile device of claim 37, wherein the PMIC comprises:

a register that stores the power management information received from the SoC via the interface connection;

a reference voltage generator that generates the reference voltage in response to a first part of the stored power management information; and

a comparator that compares the power supply voltage and the reference voltage to generate the comparison signal in response to a second part of the stored power management information controlling a hysteresis level for the comparator.

39. The mobile device of claim 38, wherein the PMIC further comprises:

a multiplexer that controls generation of the reference voltage in conjunction with the voltage reference generator, wherein the multiplexer selects one of a plurality of reference voltages as the reference voltage in response to the first part of the stored power management information.

40. The mobile device of claim 38, wherein the PMIC further comprises:

debounce logic that receives the comparison signal and generates the alarm signal by removing a bounced signal portion of the comparison signal in response to a third part of the stored power management information.

41. The mobile device of claim 40, wherein the debounce logic comprises:

a counter that decides a debounce time in response to the third part of the stored power management information and counts the comparison signal according to the decided debounce time to provide a counter output;

an AND gate that performs an AND operation on the counter output and an internal clock to generate a flip-flop control signal; and

a flip-flop gated by the comparison signal and enabled by the flip-flop control signal to generate the alarm signal.

42. The mobile device of claim 41, further comprising:

an open drain pad that receives the alarm signal from the debounce logic and provides the alarm signal to the SoC.

43. The mobile device of claim 37, wherein the SoC receives the alarm signal via a single general purpose input/output (I/O) pad.

44. The mobile device of claim 37, wherein the clock divider generates the operating clock with a first frequency before the alarm signal is received by the SoC, and generates the operating clock with a second frequency different from the first frequency after the alarm signal is received by the SoC.

46. The mobile device of claim 37, wherein the SoC further comprises a Graphics Processing Unit (GPU) that operates in response to the operating clock.

45. (canceled)

47-50. -50. (canceled)