Providing Lifetime Statistical Information For A Processor

• US 20160070321A1
• Filed: 09/10/2014
• Published: 03/10/2016
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shapira, Dorit, Rotem, Efraim, Rajwan, Doron, Shulman, Nadav, Natanzon, Esfir, Rosenzweig, Nir
• Granted Patent: US 9,904,339 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.

Claims

1. A processor comprising:

at least one core;

a power control unit (PCU) coupled to the at least one core, the PCU including a stress detector to receive at least one of a voltage and a temperature at which the processor is to operate and to calculate an effective reliability stress, and to maintain the effective reliability stress over a plurality of boot cycles;

a non-volatile storage to store the effective reliability stress; and

an interface to enable a user to access at least the effective reliability stress.

2. The processor of claim 1, wherein the stress detector includes a reliability odometer to receive the voltage and the temperature.

3. The processor of claim 1, wherein the non-volatile storage is present in a peripheral controller hub (PCH) coupled to the processor, and the PCU is to obtain the effective reliability stress from the PCH via a first message.

4. The processor of claim 1, wherein the PCU is to control a plurality of operating parameters of the processor based on the effective reliability stress and to update at least one of the plurality of operating parameters of the processor to a first degraded level when the effective reliability stress reaches a first threshold level of a plurality of threshold levels.

5. The processor of claim 1, wherein the interface comprises a universal serial bus (USB) controller to enable a USB device to communicate with the non-volatile storage.

6. The processor of claim 1, wherein the interface comprises a network interface controller to enable the user to communicate with the non-volatile storage via a remote system.

7. The processor of claim 1, wherein an embedded controller is to couple to the PCU to perform a platform level operation responsive to the effective reliability stress.

8. The processor of claim 1, wherein the PCU is to generate statistical information regarding operation of the processor and to store the statistical information in the non-volatile storage.

9. The processor of claim 8, wherein the statistical information comprises an active time of the processor and at least one parameter histogram.

10. The processor of claim 1, wherein the processor further comprises a scheduling logic to dynamically perform workload balancing between the processor and at least a second processor responsive to a management controller, the management controller to receive the effective stress reliability via the interface.

11. The processor of claim 1, wherein the stress detector includes a timer to receive processor utilization information.

12. A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

receiving, in a management entity of the machine, lifetime statistical information of a processor of a system coupled to the machine, the lifetime statistical information including an accumulated effective stress of the processor calculated within the processor, the management entity to manage a plurality of systems including the system;

determining whether the lifetime statistical information meets at least one of a plurality of thresholds, each of the plurality of thresholds related to a different characteristic of the processor; and

if the lifetime statistical information meets the at least one threshold, communicating management information to a control entity to cause the control entity to take an action with respect to the processor.

13. The machine-readable medium of claim 12, wherein the method further comprises:

communicating the management information to a node manager coupled to the system to enable the node manager to dynamically balance a workload between the processor and at least one other processor of the system responsive to the management information.

14. The machine-readable medium of claim 13, wherein the method further comprises communicating the management information to the node manager when the lifetime statistical information exceeds a thermal-related threshold.

15. The machine-readable medium of claim 12, wherein the method further comprises:

if the lifetime statistical information exceeds a lifetime-related threshold, communicating the management information to information technology personnel to request performance of a maintenance action with respect to the processor.

16. The machine-readable medium of claim 12, wherein the method further comprises:

if the lifetime statistical information exceeds a histogram-related threshold, communicating the management information to the processor to cause a power controller of the processor to update one or more operating parameter limits of the processor.

17. The machine-readable medium of claim 12, wherein the method further comprises:

storing fault information received from the processor in a debug file associated with the processor in a debug storage of the management entity; and

communicating at least a portion of the debug file to a manufacturer of the processor, wherein the management entity is a third party to the processor manufacturer.

18. A system comprising:

a processor having at least one core and a stress detector coupled to the at least one core to determine lifetime statistical information based at least in part on a voltage and a temperature at which the processor operates, a non-volatile storage to store the lifetime statistical information, and an interface to enable a user to access at least a portion of the lifetime statistical information; and

an embedded controller coupled to the processor to receive at least a portion of the lifetime statistical information and to perform a system level operation responsive thereto.

19. The system of claim 18, wherein the processor is to communicate the lifetime statistical information to a management entity of the system.

20. The system of claim 18, wherein the processor further comprises a power controller to control a plurality of operating parameters of the processor based at least in part on at least a portion of the lifetime statistical information and to update at least one of the plurality of operating parameters of the processor to a first degraded level when at least one parameter of the lifetime statistical information reaches a first threshold level of a plurality of threshold levels.

21. The system of claim 18, wherein the interface comprises a universal serial bus (USB) controller to enable a USB device to communicate with the non-volatile storage.