SEPARATE MEMORY CONTROLLERS TO ACCESS DATA IN MEMORY

• US 20160070483A1
• Filed: 05/30/2013
• Published: 03/10/2016
• Est. Priority Date: 05/30/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Yoon, Doe Hyun, Li, Sheng, Chen, Ke, Ranganathan, Parthasarathy, Chang, Jichaun, Jouppi, Norman PAul
• Granted Patent: US 10,691,344 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.

Claims

1. A system comprising:

a memory;

a first memory controller coupled to the memory;

a second memory controller separate from the first memory controller, the second memory controller to send an access command to the first memory controller, the access command to read or write data of the memory and being timing non-deterministic with respect to a timing specification of the memory,

wherein the first memory controller is responsive to the access command to issue at least one command signal to the memory, the at least one command signal satisfying the timing specification of the memory, and

wherein the first memory controller is to notify the second memory controller regarding a latency associated with accessing the memory.

2. The system of claim 1, wherein the access command is an activate command to activate a portion of the memory.

3. The system of claim 1, wherein the access command is a precharge command to precharge a portion of the memory.

4. The system of claim 1, wherein the first memory controller is to send information regarding the latency in a data packet responsive to a dummy access command from the second memory controller.

5. The system of claim 1, wherein the first memory controller is to send information regarding the latency over a handshaking signal channel between the first and second memory controllers.

6. The system of claim 1, wherein the second memory controller is to adjust scheduling of access commands for accessing data of the memory, the adjusting being responsive to the latency.

7. The system of claim 1, wherein the first memory controller is to manage ordering of responses to access commands from the second memory controller, the ordering being according to an order of the access commands received from the second memory controller.

8. The system of claim 1, wherein the first and second memory controllers are to cooperate to perform a refresh of the memory.

9. The system of claim 8, wherein the second memory controller is to issue a refresh command in response to detecting an idle period of the second memory controller, and the first memory controller is to monitor an access history of the memory, and to skip portions of the memory to refresh based on the monitored access history.

10. A method comprising:

receiving, by a device-side memory controller, an access command from a host-side memory controller, wherein the access command is timing non-deterministic with respect to a timing specification of a memory;

sending, by the device-side memory controller, at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification;

determining, by the device-side memory controller, a latency of access of the memory; and

sending, by the device-side memory controller, feedback information relating to the latency to the host-side memory controller.

11. The method of claim 10, wherein the timing specification relates to a worst-case timing parameter of the memory.

12. The method of claim 10, wherein the timing specification relates to a timing parameter associated with a power constraint of the memory.

13. The method of claim 10, further comprising:

receiving, by the host-side memory controller, a memory request from a data requester; and

in response to the memory request, sending, by the host-side memory controller, the access command to the device-side memory controller.

14. The method of claim 13, further comprising:

adjusting, by the host-side memory controller, scheduling of access commands based on the latency indicated by the feedback information.

15. An article comprising at least one machine-readable storage medium storing instructions that upon execution cause a first memory controller to:

receive a memory request from a data requester;

send an access command to a second memory controller, the access command being timing non-deterministic with respect to a timing specification of a memory, and wherein the access command is to cause the second memory controller to issue at least one access command signal to the memory that satisfies the timing specification; and

receive, from the second memory controller, information relating to a latency of accessing the memory.