DEBUG DATA SAVING IN HOST MEMORY ON PCIE SOLID STATE DRIVE

• US 20160070486A1
• Filed: 09/04/2014
• Published: 03/10/2016
• Est. Priority Date: 09/04/2014
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: HGST Netherlands B.V. (Western Digital Corporation)
• Inventors: Anderson, Michael J., Sendelbach, Lee Anton, Espeseth, Adam Michael, Schulz, Brandon William
• Granted Patent: US 10,474,618 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0778 Dumping, i.e. gathering error/state information after a fault for later diagnosis
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs

Abstract

A method, apparatus, and system are provided for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD). Upon Power Loss Interruption (PLI) event detected in a solid state drive (SSD), the SSD transfers debug data directly to the host system main (DRAM) memory via a Peripheral Component Interconnect Express (PCIE) bus.

Claims

1. A method for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD) performed by the solid state drive (SSD) and host system, said method comprising:

detecting a Power Loss Interruption (PLI) event in a solid state drive (SSD); and

transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus, responsive to the detected PLI event.

2. The method as recited in claim 1 wherein transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus includes transferring debug data to a predefined memory range in the host system main memory.

3. The method as recited in claim 2 wherein the host system main memory includes a dynamic random access memory (DRAM), and includes defining a debug buffer management device driver in a host system operating system for allocating the predefined memory range in the host system main memory including an allocated memory space having a starting memory address and a predefined memory length.

4. The method as recited in claim 1 wherein transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus includes transferring debug data to one or more predefined debug buffers in the host system main memory.

5. The method as recited in claim 1 further includes storing debug data to at least one separate non-volatile storage in the host system.

6. The method as recited in claim 1 includes reading stored debug data from the host system main memory and writing the read data to a reserved location in the solid state drive (SSD).

7. An apparatus for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD) comprising:

said solid state drive (SSD) including a controller detecting a Power Loss Interruption (PLI) event; and

said SSD transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus, responsive to the detected PLI event.

8. The apparatus as recited in claim 7 includes control code stored on a non-transitory computer readable medium, and wherein said controller and a host operating system use said control code for implementing debug data saving in host memory.

9. The apparatus as recited in claim 7 wherein the solid state drive (SSD) includes flash memory, said flash memory including one or more NAND chips.

10. The apparatus as recited in claim 7 wherein said SSD transfers debug data directly to a predefined memory range in the host system main memory.

11. The apparatus as recited in claim 7 wherein said SSD transfers debug data to one or more predefined debug buffers in the host system main memory.

12. The apparatus as recited in claim 7 further includes a host system operating system storing debug data to at least one separate host system non-volatile storage.

13. The apparatus as recited in claim 7 includes said controller reading stored debug data from the host system main memory and writing the read debug data to a reserved location in the solid state drive (SSD).

14. The apparatus as recited in claim 7 wherein said SSD transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus, responsive to the PLI event includes said SSD generating debug snapshot data saved in the solid state drive (SSD) and transferring the debug snapshot data to a predefined memory range in the host system main memory.

15. A system for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD) comprising:

a host computer;

a solid state drive (SSD);

a Peripheral Component Interconnect Express (PCIE) bus connecting said host system and said solid state drive (SSD);

said solid state drive (SSD) including a controller detecting a Power Loss Interruption (PLI) event; and

said SSD transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus, responsive to the detected PLI event.

16. The system as recited in claim 15 includes control code stored on a non-transitory computer readable medium, and wherein said controller uses said control code for implementing debug data saving.

17. The system as recited in claim 15 wherein said host system transferring drive-side cache data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus includes said SSD transferring debug data to a predefined memory range in the host system main memory.

18. The system as recited in claim 15 wherein said SSD transferring debug data directly to a host system main memory via a Peripheral Component Interconnect Express (PCIE) bus includes said SSD transferring debug data to one or more predefined debug buffers in the host system main memory.

19. The system as recited in claim 15 further includes a host system operating system storing debug data to at least one separate host system non-volatile storage.

20. The system as recited in claim 15 includes said controller reading stored debug data from the host system main memory and writing the read data to a reserved location in said solid state drive (SSD).