METHOD AND APPARATUS FOR CONFIGURING I/O CELLS OF A SIGNAL PROCESSING IC DEVICE INTO A SAFE STATE

• US 20160070619A1
• Filed: 09/10/2014
• Published: 03/10/2016
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: MORAN, ROBERT F., DEVINE, ALAN, ROBERTSON, ALISTAIR PAUL
• Granted Patent: US 9,785,508 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/0739 in a data processing system embedded in automotive or aircraft systems
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/0796 Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 2201/805 Real-time

Abstract

A peripheral integrated circuit (IC) device for providing support to a data processing IC device. The peripheral IC device comprises a fault detection component arranged to detect an occurrence of fault conditions within the data processing IC device. The peripheral IC device further comprises a safe state control component. Upon detection of a fault condition occurring within the data processing IC device by the fault detection component, the safe state control component is arranged to cause at least one I/O cell of the data processing IC device to be configured into at least one scan-chain, and cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

Claims

1. A peripheral integrated circuit, IC, device for providing support to at least one data processing IC device, the peripheral IC device comprising:

at least one fault detection component arranged to detect an occurrence of at least one fault condition within the at least one data processing IC device; and

at least one safe state control component arranged to, upon detection of at least one fault condition occurring within the at least one data processing IC device by the at least one fault detection component;

cause at least one input/output, I/O, cell of the at least one data processing IC device to be configured into at least one scan-chain; and

cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into a state corresponding to the predefined control signal.

2. The peripheral IC device of claim 1, wherein the peripheral IC device is arranged to be operably coupled to the at least one data processing IC device via a serial peripheral interface, and the at least one safe state control component is arranged to transmit command signals to the at least one data processing IC device to cause the at least one I/O cell of the at least one data processing IC device to be configured into at least one scan-chain and to cause the at least one predefined control signal to be scanned into the at least one scan-chain via the serial peripheral interface.

3. The peripheral IC device of claim 1, wherein the at least one safe state control component is arranged to cause the at least one I/O cell of the at least one data processing IC device to be configured into at least one scan-chain by sending at least one command signal to at least one debug component of the at least one data processing IC device instructing the debug component to configure the at least one I/O cell of the at least one data processing IC device into at least one scan-chain.

4. The peripheral IC device of claim 3, wherein the at least one safe state control component is arranged to cause at least one predefined control signal to be scanned into the at least one scan-chain by sending at least one command signal to the at least one debug component of the at least one data processing IC device comprising at least one control signal pattern to cause the at least one debug component to scan in at least one control signal into the at least one scan-chain to configure the at least one I/O cell to comprise at least one logical level corresponding to the at least one control signal pattern.

5. The peripheral IC device of claim 3, wherein the at least one safe state control component is arranged to cause at least one predefined control signal to be scanned into the at least one scan-chain by sending at least one command signal to the at least one debug component of the at least one data processing IC device to cause the at least one debug component to scan in at least one control signal into the at least one scan-chain to configure the at least one I/O cell to comprise a high input impedance.

6. The peripheral IC device of claim 3, wherein the at least one safe state control component is arranged to cause at least one predefined control signal to be scanned into the at least one scan-chain by sending at least one command signal to the at least one debug component of the at least one data processing IC device to cause the at least one debug component to scan in at least one control signal into the at least one scan-chain to configure the at least one I/O cell to comprise at least one logical level corresponding to at least one predefined control signal pattern.

7. The peripheral IC device of claim 3, wherein the at least one safe state control component is operably coupled to at least one memory element and arranged to read therefrom at least one series of command signals for causing the at least one I/O cell of the at least one data processing IC device to be configured into at least one scan-chain and for causing at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into to a state corresponding to the predefined control signal.

8. The peripheral IC device of claim 7, wherein the at least one safe state control component is further arranged to read from the at least one memory element the at least one control signal to be scanned into the at least one scan-chain.

9. The peripheral IC device of claim 3, wherein the at least one safe state control component is operably coupled to at least one fuse element configurable to define the at least one control signal to be scanned into the at least one scan-chain.

10. The peripheral IC device of claim 3, wherein the at least one control signal to be scanned into the at least one scan-chain is hardcoded into the peripheral IC device.

11. The peripheral IC device of claim 1, wherein the at least one predefined control signal to be scanned into the at least one scan-chain is arranged to force the at least one I/O cell into to a state comprising at least one of:

a high logical level;

a low logical level; and

a high input impedance level.

12. The peripheral IC device of claim 1, wherein the at least one fault detection component is arranged to detect the occurrence of at least one of:

an over-current condition within the data processing IC device;

an over-voltage condition within the data processing IC device;

an over-temperature condition within the data processing IC device; and

a watchdog function not being serviced.

13. The peripheral IC device of claim 1, wherein the at least one fault detection component is arranged to detect the occurrence of fault conditions based on a notification received from the data processing IC device of the detection of a fault condition thereby.

14. The peripheral IC device of claim 1, wherein the support provided by the peripheral IC device to the at least one data processing IC device comprises at least one from a group comprising at least one of:

power regulator functionality;

over current detection functionality;

watchdog functionality; and

physical layer communication functionality.

15. A data processing integrated circuit, IC, device comprising at least one safety level configuration component, the at least one safety level configuration component being controllable by at least one peripheral IC device according to any one of the preceding claims operably coupled to the data processing IC device to:

configure at least one input/output, I/O, cell of the at least on data processing IC device to be configured into at least one scan-chain; and

cause at least one predefined control signal to be scanned into the at least one scan-chain to configure the at least one I/O cell into to a state corresponding to the predefined control signal.

16. The data processing IC device of claim 15, wherein the at least one I/O cell is arranged to be isolated from core functional components of the data processing IC device when configured into the at least one scan-chain by the at least one safety level configuration component.

17. The data processing IC device of claim 15, wherein the at least one safety level configuration component comprises at least one debug component of the data processing IC device.

18. The data processing IC device of claim 15, wherein the at least one scan-chain comprises at least one boundary scan scan-chain.

19. The data processing IC device of claim 15, wherein the data processing IC device comprises a microprocessor.

20. A data processing system comprising at least one data processing integrated circuit device and at least one peripheral integrated circuit device according to claim 1 for providing support to the at least one data processing integrated circuit device.