SYSTEM AND METHOD OF COUNTING PROGRAM/ERASE CYCLES

• US 20160070643A1
• Filed: 09/08/2014
• Published: 03/10/2016
• Est. Priority Date: 09/08/2014
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: SHEN, ZHENLEI
• Application Number:
  US14/480,306
• Publication Number:
  US 20160070643A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0035 Evaluating degradation, retention or wearout, e.g. by counting writing cycles
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A method includes, in a data storage device that includes a memory, detecting an operation associated with a block of the memory. The operation is associated with a program/erase cycle. The method further includes, responsive to detecting the operation, performing a comparison between a random number and at least one value of a set of values. The method includes selectively adjusting a value of a counter associated with the block based on the comparison.

Claims

1. A method comprising:

in a data storage device that includes a memory, performing

detecting an operation associated with a block of the memory, the operation associated with a program/erase cycle;

responsive to detecting the operation, performing a comparison between a random number and at least one value of a set of values; and

selectively adjusting a value of a counter associated with the block based on the comparison.

2. The method of claim 1, wherein the counter is configured to track a portion of a total number of program/erase cycles by selectively adjusting the value of the counter based on generated random numbers.

3. The method of claim 1, wherein the operation is a write operation or an erase operation.

4. The method of claim 1, further comprising identifying a mode associated with the block.

5. The method of claim 4, wherein the mode is a single-level cell (SLC) mode or a multi-level cell (MLC) mode.

6. The method of claim 4, wherein the random number is generated to be constrained within a range, and wherein the range is selected based on the mode.

7. The method of claim 4, further comprising selecting the set of values based on the mode.

8. The method of claim 1, wherein the value of the counter is adjusted when the random number matches a value of the set of values.

9. The method of claim 1, wherein the set of values includes multiple values.

10. The method of claim 1, wherein the set of values includes fewer than two values.

11. The method of claim 10, wherein set of values includes a single value that is a threshold value, and wherein the counter is adjusted when the random number satisfies the threshold value.

12. The method of claim 1, wherein the memory is a flash memory.

13. The method of claim 1, wherein the memory includes a resistive random access memory (ReRAM).

14. The method of claim 1, wherein the memory includes a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device includes circuitry associated with operation of the memory cells.

15. A data storage device comprising:

a memory including a block, wherein the block is associated with a counter; and

a controller coupled to the memory, wherein the controller is configured to detect an operation associated with the block, wherein the operation is associated with a program/erase cycle, and wherein, responsive to detecting the operation, the controller is configured to perform a comparison between a random number and at least one value of a set of values and to adjust a value of the counter based on the comparison.

16. The data storage device of claim 15, wherein the controller is configured to identify whether the block is operating in a single-level cell (SLC) mode or a multi-level cell (MLC) mode.

17. The data storage device of claim 16, wherein, when the block is operating in the SLC mode, the random number is generated to be constrained within a first range, and wherein, when the block is operating in the MLC mode, the random number is generated to be constrained within a second range.

18. The data storage device of claim 17, wherein the first range is larger than the second range.

19. The data storage device of claim 16, wherein the controller is configured to select a first set of values or a second set of values to be used as the set of values, wherein the first set of values is selected when the block is operating in the SLC mode, and wherein the second set of values is selected when the block is operating in the MLC mode.

20. The data storage device of claim 19, wherein the first set of values includes more values than second set of values.

21. The data storage device of claim 15, wherein the memory includes a resistive random access memory (ReRAM).

22. The data storage device of claim 15, wherein the memory includes a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the memory includes circuitry associated with operation of the memory cells.

23. A data storage device comprising:

a memory including a block, wherein the block is associated with a counter; and

a controller coupled to the memory, wherein the controller is configured to detect an operation associated with the block, wherein the operation is associated with a program/erase cycle, and wherein, responsive to detecting the operation, the controller is configured to perform a comparison between a random number and at least one value of a set of values and to adjust a value of the counter based on the comparison,

wherein the random number is constrained within a first range when the block is operating in a single-level cell (SLC) mode and wherein the random number is constrained within a second range when the block is operating in a multi-level cell (MLC) mode, and wherein the first range is larger than the second range.

24. The data storage device of claim 23, wherein the memory includes a flash memory.

25. The data storage device of claim 23, wherein the memory includes a resistive random access memory (ReRAM).

26. A data storage device comprising:

a memory including a block, wherein the block is associated with a counter; and

a controller coupled to the memory, wherein the controller is configured to detect an operation associated with the block, wherein the operation is associated with a program/erase cycle, and wherein, responsive to detecting the operation, the controller is configured to perform a comparison between a random number and at least one value of a set of values and to adjust a value of the counter based on the comparison,

wherein the set of values is a first set of values when the block is operating in a single-level cell (SLC) mode and wherein the set of values is a second set of values when the block is operating in a multi-level cell (MLC) mode, and wherein the first set of values includes more values than the second set of values.

27. The data storage device of claim 26, wherein the memory includes a flash memory.

28. The data storage device of claim 26, wherein the memory includes a resistive random access memory (ReRAM).