RESETTING MEMORY LOCKS IN A TRANSACTIONAL MEMORY SYSTEM

• US 20160070660A1
• Filed: 09/10/2014
• Published: 03/10/2016
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: FONTENOT, NATHAN, GRIMM, RYAN PATRICK, JENNINGS, ROBERT CORY Jr., SCHOPP, JOEL HOWARD, STROSAKER, MICHAEL THOMAS
• Granted Patent: US 9,524,246 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 12/1475 in a virtual system, e.g. with translation means
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 2205/067 Bidirectional FIFO, i.e. system allowing data transfer in two directions
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.

Claims

1-7. -7. (canceled)

8. A data processing system comprising:

at least one memory;

one or more processors in communication with the memory, the processors operable to execute instructions which cause the processor to;

set at least one new memory lock during execution of a transaction that acquires access to a region of memory, the new memory lock indicating that the transaction and its associated thread has exclusive temporary access to the memory region;

determine if a first in first out (FIFO) memory lock register is full of memory locks; and

in response to the FIFO memory lock register being full;

remove a memory lock from a tail position of the FIFO memory lock register;

reset the removed memory lock to return to a transactional memory state; and

add the new memory lock to a head position in the FIFO memory lock register.

9. The data processing system of claim 8, further comprising instructions that cause the processor to:

determine if an existing memory lock contained within the current FIFO memory lock register is a same lock as the new memory lock; and

in response to determining that an existing memory lock contained within the FIFO memory lock register is the same as the new memory lock being added to the FIFO memory lock register, remove and discard the existing memory lock from a current position in the FIFO memory lock register.

10. The data processing system of claim 8, further comprising instructions that cause the processor to:

shift at least one existing memory lock having a higher position in the FIFO memory lock register than the removed memory lock one position towards the tail position of the FIFO memory lock register prior to adding the new memory lock to the head position of the FIFO memory lock register.

11. The data processing system of claim 8, further comprising instructions that cause the processor to:

prior to adding the new memory lock to the head position of the FIFO memory lock register, shift each other remaining memory lock in the FIFO memory lock register one position towards the tail position in the FIFO memory lock register.

12. The data processing system of claim 8, wherein resetting the removed memory lock to return to a transactional memory state allows access to the associated region of memory by a next requesting transaction.

13. The data processing system of claim 8, further comprising instructions that cause the processor to:

in response to the FIFO memory lock register not being full;

shift at least one existing memory lock in the FIFO memory lock register one position towards the tail position of the FIFO memory lock register; and

add the new memory lock to the head position of the FIFO memory lock register.

14. The data processing system of claim 8, wherein the processor further comprises a memory lock module that includes the FIFO memory lock register.

15. A computer program product comprising:

a computer readable storage device; and

program code on the computer readable storage device that when executed within a processing device, the program code provides the functionality of;

setting at least one new memory lock during execution of a transaction that acquires access to a region of memory, the new memory lock indicating that the transaction and its associated thread has exclusive temporary access to the memory region;

determining if a first in first out (FIFO) memory lock register is full of memory locks; and

in response to the FIFO memory lock register being full;

removing a memory lock from a tail position of the FIFO memory lock register;

resetting the removed memory lock to return to a transactional memory state; and

adding the new memory lock to a head position in the FIFO memory lock register.

16. The computer program product of claim 15, further comprising program code on the computer readable storage device that when executed within the processing device, the program code provides the functionality of:

determining if an existing memory lock contained within the current FIFO memory lock register is a same lock as the new memory lock; and

in response to determining that an existing memory lock contained within the FIFO memory lock register is the same as the new memory lock being added to the FIFO memory lock register, removing and discarding the existing memory lock from a current position in the FIFO memory lock register.

17. The computer program product of claim 15, further comprising program code on the computer readable storage device that when executed within the processing device, the program code provides the functionality of:

shifting at least one existing memory lock having a higher position in the FIFO memory lock register than the removed memory lock one position towards the tail position of the FIFO memory lock register prior to adding the new memory lock to the head position of the FIFO memory lock register.

18. The computer program product of claim 15, further comprising program code on the computer readable storage device that when executed within the processing device, the program code provides the functionality of:

prior to adding the new memory lock to the head position of the FIFO memory lock register, shifting each other remaining memory lock in the FIFO memory lock register one position towards the tail position in the FIFO memory lock register.

19. The computer program product of claim 15, wherein resetting the removed memory lock to return to a transactional memory state allows access to the associated region of memory by a next requesting transaction.

20. The computer program product of claim 15, further comprising program code on the computer readable storage device that when executed within the processing device, the program code provides the functionality of:

in response to the FIFO memory lock register not being full;

shifting at least one existing memory lock in the FIFO memory lock register one position towards the tail position of the FIFO memory lock register; and

adding the new memory lock to the head position of the FIFO memory lock register.