DEVICES AND METHODS FOR REDUCING OR ELIMINATING MURA ARTIFACT ASSOCIATED WITH WHITE IMAGES
First Claim
1. A method, comprising:
- generating a first gate signal to be supplied to a first gate of a first transistor;
generating a second gate signal to be supplied to a second gate of a second transistor; and
adjusting a falling edge rate of the first gate signal to reduce a voltage drop associated with pixels of a display panel, wherein adjusting the falling edge rate of the first gate signal comprises decreasing the falling edge rate of the first gate signal during a period of time in which the first gate signal falls and the second gate signal rises to prevent an occurrence of an image artifact on the display panel.
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Accused Products
Abstract
Devices and methods for reducing or eliminating image artifacts are provided. By way of example, a method of preventing an occurrence of an image artifact on a display panel may include generating a first gate signal to be supplied to a first gate of a first transistor, generating a second gate signal to be supplied to a second gate of a second transistor, and adjusting a falling edge rate of the first gate signal or a rising edge rate of the second gate signal to reduce a voltage drop associated with row pixels of the display panel. Adjusting the falling edge rate of the first gate signal or the rising edge rate of the second gate signal include decreasing the falling edge rate of the first gate signal or the rising edge rate of the second gate signal during a period of time in which the first gate signal falls.
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Citations
30 Claims
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1. A method, comprising:
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generating a first gate signal to be supplied to a first gate of a first transistor; generating a second gate signal to be supplied to a second gate of a second transistor; and adjusting a falling edge rate of the first gate signal to reduce a voltage drop associated with pixels of a display panel, wherein adjusting the falling edge rate of the first gate signal comprises decreasing the falling edge rate of the first gate signal during a period of time in which the first gate signal falls and the second gate signal rises to prevent an occurrence of an image artifact on the display panel. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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generating a first gate signal to be supplied to a first gate of a first transistor; generating a second gate signal to be supplied to a second gate of a second transistor; and adjusting a rising edge rate of the second gate signal to reduce a voltage drop associated with pixels of a display panel, wherein adjusting the rising edge rate of the second gate signal comprises decreasing the rising edge rate of the second gate signal during a period of time in which the first gate signal falls and the second gate signal rises to prevent an occurrence of an image artifact on the display panel. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. An electronic device, comprising:
gate line driving circuitry, comprising; a first transistor configured to receive a first signal, wherein the first transistor is configured to activate during a positive cycle of the first signal, and wherein the first transistor is configured to cause the gate line driving circuitry to generate a first gate signal; a second transistor coupled in series to the first transistor and configured to receive the first signal, wherein the second transistor is configured to activate during a negative cycle of the first signal, and wherein the second transistor is configured to cause the gate line driving circuitry to generate a second gate signal; and a first diode coupled to the first transistor and a second diode coupled to the second transistor, wherein the first diode and the second diode are configured to provide a current discharge path to control a rate at which the first gate signal falls or the second gate signal rises. - View Dependent Claims (18, 19, 20, 21)
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22. An electronic display, comprising:
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a pixel, including; a pixel electrode; a first thin-film transistor (TFT) having a first source coupled to a data line and a first gate coupled to a first gate line; a second TFT having a second source coupled to a first drain of the first TFT, a second gate coupled to a second gate line, and a second drain coupled to the pixel electrode, wherein the first TFT and the second TFT are configured to pass image data to the pixel electrode; and gate driver circuitry configured to supply a first gate signal to the first gate line and a second gate signal to the second gate line, wherein the gate driver circuitry is configured to modulate the second gate signal between a voltage substantially equal to and a voltage less than that of the first gate signal. - View Dependent Claims (23, 24, 25, 26)
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27. A display panel, comprising:
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a pixel array comprising a plurality of pixels; and a gate driver configured to; provide a first set of activation signals to a first set of the plurality of pixels; provide a second set of activation signals to a second set of the plurality of pixels; and adjust a falling edge rate of the first set of activation signals or a rising edge rate of the second set of activation signals to reduce a voltage drop associated with row common voltage electrodes (VCOMs) of the display panel, wherein adjusting the falling edge rate of the first set of activation signals or the rising edge rate of the second set of activation signals comprises delaying the falling edge rate of the first set of activation signals or the rising edge rate of the second set of activation signals during a period of time in which the first set of activation signals falls and the second set of activation signals rises. - View Dependent Claims (28, 29, 30)
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Specification