VOLTAGE GENERATING CIRCUIT

• US 20160071554A1
• Filed: 11/18/2015
• Published: 03/10/2016
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HONG, Hyun-Sung
• Granted Patent: US 9,558,792 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line coupled with a first terminal of the sense amplifier, and a second data line coupled with a second terminal of the sense amplifier. The second type is different from the first type. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage.

Claims

1. A circuit comprising:

a first transistor of a first type;

a second transistor of a second type different from the first type;

a sense amplifier;

a first data line coupled with a first terminal of the sense amplifier; and

a second data line coupled with a second terminal of the sense amplifier,

wherein

a first terminal of the first transistor is configured to receive a supply voltage;

a second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, and a third terminal of the second transistor are coupled together and are configured to carry a voltage;

a first terminal of the second transistor is configured to receive a reference voltage; and

the first data line and the second data line are configured to receive a voltage value of the voltage.

2. The circuit of claim 1, wherein

the sense amplifier comprises a first inverter and a second inverter that form a cross latch;

the first inverter has a first voltage transfer curve;

the second inverter has a second voltage transfer curve;

the first voltage transfer curve and the second voltage transfer curve include a cross point; and

the voltage value of the voltage is selected based on at least one of a size of the first transistor, a size of the second transistor, or the cross point.

3. The circuit of claim 2, wherein

the cross point and an origin of a first coordinate and a second coordinate of the first and second voltage transfer curves form a line;

and

the voltage value of the voltage is on the line.

4. The circuit of claim 2, wherein a voltage value of the cross point varies along with the voltage value of the voltage as a function of process variations.

5. The circuit of claim 1, wherein

the sense amplifier includes an inverter, the inverter comprising a third transistor of the first type coupled in series with a fourth transistor of the second type;

and

both the voltage and a voltage transfer curve of the inverter vary as a function of process variations.

6. The circuit of claim 1, further comprising an operational amplifier configured to supply the voltage value to the first data line and the second data line.

7. The circuit of claim 1, wherein the voltage value is about half a value of the supply voltage for a first process corner, less than half a value of the supply voltage for a second process corner, and greater than half a value of the supply voltage for a third process corner.

8. A circuit comprising:

a sense amplifier;

a first data line coupled with a first terminal of the sense amplifier;

a second data line coupled with a second terminal of the sense amplifier; and

a voltage generating circuit configured to provide a pre-charge voltage to the first data line and the second data line, the pre-charge voltage having a self-adjusting voltage value based on a process corner.

9. The circuit of claim 8, wherein

the sense amplifier includes a first inverter and a second inverter that form a cross latch;

the first inverter has a first voltage transfer curve;

the second inverter has a second voltage transfer curve;

the first voltage transfer curve and the second voltage transfer curve include a cross point; and

the self-adjusting voltage value is selected based on the cross point.

10. The circuit of claim 9, wherein

the cross point and an origin of a first coordinate and a second coordinate of the first and second voltage transfer curves form a line;

and

the self-adjusting voltage value is on the line.

11. The circuit of claim 9, wherein a voltage value of the cross point varies along with the self-adjusting voltage based on the process corner.

12. The circuit of claim 8, wherein the voltage generating circuit comprises an inverter having an input coupled with an output, and the self-adjusting voltage value is provided at the output.

13. The circuit of claim 8, wherein

the voltage generating circuit comprises an inverter,

the inverter comprises a first transistor of a first type coupled in series with a second transistor of a second type different from the first type, and

the inverter is configured to generate the self-adjusting voltage from an equilibrium condition in which a current through the first transistor is equal to a current through the second transistor.

14. The circuit of claim 8, wherein the sense amplifier comprises an inverter, and a voltage transfer curve of the inverter varies based on the process corner.

15. The circuit of claim 8, further comprising an operational amplifier configured to supply the self-adjusting voltage value to the first data line and the second data line.

16. The circuit of claim 8, wherein the self-adjusting voltage value is about half a value of the supply voltage when the process corner is a first process corner, less than half a value of the supply voltage when the process corner is a second process corner, and greater than half a value of the supply voltage when the process corner is a third process corner.

17. A method comprising:

providing a self-adjusting voltage with a first inverter having an input coupled with an output, the self-adjusting voltage having different voltage values in different process corners;

pre-charging a pair of data lines with the self-adjusting voltage in a first time period; and

causing a bit line split between the data lines to develop in a second time period,

wherein

in both the first time period and the second time period, a first voltage value of the different voltage values in a first process corner is self-adjustable to a second voltage value of the different voltage values in a second process corner.

18. The method of claim 17, wherein providing the self-adjusting voltage with the first inverter comprises:

receiving a supply voltage at a first terminal of a first transistor of a first type;

receiving a reference supply voltage at a first terminal of a second transistor of a second type different from the first type, the first transistor and the second transistor configured in series; and

from an equilibrium condition in which a current through the first transistor is equal to a current through the second transistor, generating the self-adjusting voltage at an output of the first inverter coupled to an input of the first inverter.

19. The method of claim 17, wherein causing the bit line split comprises causing the bit line split with a sense amplifier, the sense amplifier comprising a second inverter having a voltage transfer curve that varies based on the first process corner and the second process corner.

20. The method of claim 17, wherein the different voltage values include about half a value of a supply voltage, less than half a value of the supply voltage, and greater than half a value of the supply voltage.