Semiconductor Device and Manufacturing Method Thereof

• US 20160071778A1
• Filed: 05/20/2015
• Published: 03/10/2016
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: OTSUBO, Yoshitaka, YOSHIDA, Hiroshi, FUJINO, Junji, KIKUCHI, Masao, MURAI, Junichi
• Granted Patent: US 9,443,778 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/52 Mounting semiconductor bodies in containers
• CPC Class Codes: H01L 21/54 Providing fillings in containers, e.g. gas fillings
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4846 with multiple bonds on the same bonding area
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/85801 : Soldering or alloying
• CPC Class Codes: H01L 23/053 : the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/24 : solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/29 : characterised by the material , e.g. carbon interlayer dielectrics H01L23/5329
• CPC Class Codes: H01L 23/3178 : Coating or filling in grooves made in the semiconductor body
• CPC Class Codes: H01L 23/32 : Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/3735 : Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4006 : with bolts or screws
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/1203 : Rectifying Diode
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/2076 : equal to or larger than 100 microns
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

It is possible to provide a semiconductor device which can be obtained at a high reliability by warping an insulating substrate stably into a convex shape while ensuring a close contact between a cooling member and the insulating substrate. The semiconductor device includes an insulating substrate, a semiconductor element disposed on a first surface of the insulating substrate, a case connected to the insulating substrate, and a resin filled inside the case. Assuming that the thickness of the insulating substrate is denoted by t1, the thickness of the resin is denoted by t2, the linear expansion coefficient of the insulating substrate is denoted by α1, and the linear expansion coefficient of the resin is denoted by α2, the relationship therebetween satisfies t2≧t1 and α2≧α1, and a second surface of the insulating substrate opposite to the first surface thereof is warped into a convex shape.

Claims

1. A semiconductor device comprising:

an insulating substrate;

a semiconductor element disposed on a first surface of said insulating substrate;

a case connected to said insulating substrate and configured to accommodate therein said semiconductor element; and

a resin filled inside said case so as to bury said semiconductor element,

assuming that the thickness of said insulating substrate is denoted by t1, the thickness of said resin is denoted by t2, the linear expansion coefficient of said insulating substrate is denoted by α

1, and the linear expansion coefficient of said resin is denoted by α

2, the relationship therebetween satisfying t2≧

t1 and α

2≧

α

1, and

a second surface of said insulating substrate opposite to said first surface thereof being warped into a convex shape.

2. The semiconductor device according to claim 1, wherein

said case is provided with an overlapping portion that overlaps with an outer edge of said insulating substrate in planar view, and an extending portion that extends from said overlapping portion outward than said outer edge of said insulating substrate,

said semiconductor device further includes a securing member configured to secure said extending portion of said case to an external member located external to said semiconductor device,

said overlapping portion is provided with a stepped portion so as to accommodate said outer edge of said insulating substrate, and

the depth of said stepped portion is smaller than the sum of the thickness of said insulating substrate and an amount of warpage of said insulating substrate in a state where said outer edge of said insulating substrate has not yet been pressed by said stepped portion of said case.

3. The semiconductor device according to claim 2, wherein

said case is elastically deformed when it is secured to said external member by using said securing member in a state where said outer edge of said insulating substrate is sandwiched between said overlapping portion and said external member.

4. The semiconductor device according to claim 1, wherein

said case is provided with an overlapping portion that overlaps with an outer edge of said insulating substrate in planar view,

a through hole is formed to penetrate said overlapping portion of said case and said outer edge of said insulating substrate, and

said semiconductor device further includes a securing member inserted into said through hole so as to secure said outer edge of said insulating substrate and said overlapping portion to an external member located external to said semiconductor device.

5. A manufacturing method of a semiconductor device, comprising:

a step of disposing a semiconductor element on a first surface of an insulating substrate and preparing a case connected to said insulating substrate and configured to accommodate therein said semiconductor element; and

a step of filling a resin into said case so as to bury therein said semiconductor element,

assuming that the thickness of said insulating substrate is denoted by t1, the thickness of said resin is denoted by t2, the linear expansion coefficient of said insulating substrate is denoted by α

1, and the linear expansion coefficient of said resin is denoted by α

2, the relationship therebetween satisfying t2≧

t1 and α

2≧

α

1, and

after the step of filling said resin, a second surface of said insulating substrate opposite to said first surface thereof being warped into a convex shape.

6. The manufacturing method of a semiconductor device according to claim 5 further comprising:

a step of connecting said second surface of said insulating substrate opposite to said first surface thereof to an external member located external to said semiconductor device after the step of filling said resin, wherein

in the preparing step, said case is provided with an overlapping portion that overlaps with an outer edge of said insulating substrate in planar view and an extending portion that extends from said overlapping portion outward than said outer edge of said insulating substrate,

said overlapping portion is provided with a stepped portion so as to accommodate said outer edge of said insulating substrate, and

the depth of said stepped portion is smaller than the sum of the thickness of said insulating substrate and an amount of warpage of said insulating substrate in a state where said outer edge of said insulating substrate has not yet been pressed by said stepped portion of said case, and

in the connecting step, said extending portion of said case is secured to said external member by using a securing member.

7. The manufacturing method of a semiconductor device according to claim 6, wherein

in the connecting step, said case is elastically deformed when it is secured to said external member by using said securing member in a state where said outer edge of said insulating substrate is sandwiched between said overlapping portion and said external member.

8. The manufacturing method of a semiconductor device according to claim 5 further comprising:

a step of connecting said second surface of said insulating substrate opposite to said first surface thereof to an external member located external to said semiconductor device after the step of filling said resin, wherein

in the preparing step, said case is provided with an overlapping portion that overlaps with an outer edge of said insulating substrate in planar view, and

a through hole is formed to penetrate said overlapping portion of said case and said outer edge of said insulating substrate,

in the connecting step, said securing member is inserted into said through hole so as to secure said outer edge of said insulating substrate and said overlapping portion to said external member.