SEMICONDUCTOR MEMORY DEVICE

• US 20160071870A1
• Filed: 02/24/2015
• Published: 03/10/2016
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MINAMI, Toshifumi, SATO, Atsuhiro, YONEHAMA, Keisuke, BABA, Yasuyuki, SHINOHARA, Hiroshi, KAMATA, Hideyuki, HIGASHITSUJI, Teppei
• Granted Patent: US 9,893,078 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/00 EEPROM devices comprising charge-trapping gate insulators
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Claims

1. A semiconductor memory device comprising:

a conducting layer and an insulating layer that are disposed above a semiconductor substrate;

a plurality of pillars that extend in a first direction which crosses a surface of the semiconductor substrate; and

a plate that is disposed between the plurality of pillars and extends in the first direction,

wherein a surface of the plate, which faces the pillars, has convex portions and non-convex portions.

2. The device according to claim 1,

wherein respective center points of the convex portions of the plate and respective center points of the pillars are disposed in a regular array above the surface of the semiconductor substrate.

3. The device according to claim 2,

wherein a first distance between a center point of the convex portion of the plate and a center point of the pillar adjacent to the convex portion is substantially equal to a second distance between the respective center points of the adjacent pillars.

4. The device according to claim 3,

wherein a third distance between the respective center points of adjacent convex portions is substantially equal to the first and second distances.

5. The device according to claim 1, further comprising:

an insulating film that surrounds each of the pillars,

wherein a gap between a convex portion of the plate and the insulating film of the pillar adjacent to the convex portion is smaller than a gap between a non-convex portion of the plate and the insulating film of the pillar adjacent to the non-convex portion.

6. The device according to claim 1, further comprising:

an insulating film that surrounds each of the pillars,

wherein the convex portion of the plate has substantially the same dimensions and materials as the pillar and the insulating film.

7. The device according to claim 1, wherein the non-convex portions each have a substantially flat surface facing a pillar adjacent thereto.

8. The device according to claim 1, further comprising:

a back gate layer in contact with the surface of the semiconductor substrate;

a lower insulating layer between the conducting layer and the back gate layer; and

an etch stop layer formed in the lower insulating layer, the plate extending through the conducting layer and the insulating layer and stopping at the etch stop layer.

9. The device according to claim 8, further comprising:

a selection gate layer above the conducting layer and the insulating layer,

wherein the plate extends through the selection gate layer.

10. The device according to claim 9, further comprising:

a plurality of additional conducting layers and additional insulating layers alternately stacked between the selection gate layer and the lower insulating layer,

wherein the plate extends through the additional conducting layers and the additional insulating layers.

11. A method of manufacturing a semiconductor memory device having a conducting layer and an insulating layer that are disposed above a semiconductor substrate, said method comprising:

forming a plurality of rows of holes that are evenly spaced apart from each other through the conducting layer and the insulating layer;

disposing a plurality of pillars each containing a center pillar surrounded by an insulating film in the holes;

forming a plurality of openings between each pair of pillars in alternating rows; and

filling the openings with insulating material.

12. The method of claim 11, wherein the holes are formed to be substantially circular.

13. The method of claim 11, wherein the holes are formed in an oval shape.

14. The method of claim 11, wherein a material of the center pillar in each of the pillars is the same.

15. The method of claim 11, wherein a surface of the openings facing pillars of an adjacent row is flat.

19. The method of claim 11, wherein the holes and the opening are formed using two masks.

20. The method of claim 11, wherein the holes and the opening are formed using a single mask.

16. The method of claim 16, further comprising:

forming an etch stop layer above the semiconductor substrate,

wherein the holes in the alternating rows and the openings are formed to expose the etch stop layer.

17. The method of claim 16, wherein the semiconductor memory device has a back gate layer in contact with the semiconductor substrate and a lower insulating layer between the conducting layer and the back gate layer, and the etch stop layer is formed in the lower insulating layer.

18. The method of claim 16, wherein the semiconductor memory device has a selection gate layer above the conducting layer and the insulating layer, and the holes in the alternating rows and the openings are formed to extend through the selection gate layer.