Symmetric Linear Equalization Circuit with Increased Gain

• US 20160072449A1
• Filed: 09/29/2015
• Published: 03/10/2016
• Est. Priority Date: 05/16/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Granted Patent: US 9,419,564 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/301 the loading circuit of an amplifying stage comprising a coil
• CPC Class Codes: H03F 2200/366 Multiple MOSFETs are coupled in parallel
• CPC Class Codes: H03F 2203/45022 One or more added resistors to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals

Abstract

Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals.

Claims

1. A method comprising:

receiving first and second input signals at non-inverting inputs of first and second amplifier elements, respectively, the first and second input signals corresponding to symbols of a codeword;

cross-coupling the first and second input signals to frequency-dependent inverting inputs of the second and first amplifier elements, respectively; and

,

generating an amplified codeword identification signal using the first and second amplifier elements, the first and second amplifier elements providing a gain corresponding to a combination of common-source gain and common-gate gain, the common-source gain applied to the non-inverting inputs and the common-gate gain applied to the inverting inputs, the amplified codeword identification signal used at least in part to determine a set of output bits represented by the symbols of the codeword.

2. The method of claim 1, wherein the symbols have values selected from a set of at least three values.

3. The method of claim 1, wherein the first and second input signals are each cross-coupled to the frequency-dependent inverting inputs via respective series capacitors.

4. The method of claim 1, wherein the first and second amplifier elements are MOS transistors.

5. The method of claim 1, wherein the first and second input signals are received from a multi-wire bus.

6. The method of claim 1, wherein the first and second amplifier elements are arranged in a differential amplifier configuration.

7. The method of claim 1, wherein the amplified codeword identification signal is part of a set of amplified codeword identification signals used to fully determine the set of output bits.

8. A method comprising:

receiving first and third input signals at respective non-inverting inputs of a first pair of amplifier elements within a first amplifier branch connected to a first load impedance element, the first and third input signals corresponding to symbols of a codeword of a vector signaling code;

receiving second and fourth input signals at respective non-inverting inputs of a second pair of amplifier elements within a second amplifier branch connected to a second load impedance element, the second and fourth signals corresponding to symbols of the codeword;

cross-coupling the first and third input signals to respective frequency-dependent inverting inputs of the second pair of amplifier elements;

cross-coupling the second and fourth input signals to respective frequency-dependent inverting inputs of the first pair of amplifier elements;

generating an amplified codeword identification signal using the first and second amplifier branches, the first and second amplifier branches providing a gain corresponding to a combination of common-source gain and common-gate gain, the common-source gain applied to the non-inverting inputs and the common-gate gain applied to the inverting inputs, the amplified codeword identification signal used at least in part to determine a set of output bits represented by the symbols of the codeword.

9. The method of claim 8, wherein the vector signaling code is an H4 code.

10. The method of claim 9, wherein the codeword is a permutation of a vector ±

{1 −

1/3 −

1/3 −

1/3}.

11. The method of claim 8, wherein the amplified codeword identification signal is part of a set of amplified codeword identifications signals used to determine the set of output bits.

12. The method of claim 11, wherein a set of three amplified codeword identification results are used to fully determine the set of output bits.

13. The method of claim 11, wherein the first, second, third and fourth input signals are received via a multi-wire bus.

14. An apparatus comprising:

first and second amplifier elements configured to (i) receive first and second input signals at non-inverting inputs, respectively, and (ii) cross-couple the first and second input signals to frequency-dependent inverting inputs of the second and first amplifier elements, respectively, the first and second input signals corresponding to symbols of a codeword; and

,

a pair of load impedance elements connected to the first and second amplifier elements configured to generate an amplified codeword identification signal, the first and second amplifier elements configured to provide a gain corresponding to a combination of common-source gain and common-gate gain, the common-source gain applied to the non-inverting inputs and the common-gate gain applied to the frequency-dependent inverting inputs, the amplified codeword identification signal used at least in part to determine a set of output bits represented by the symbols of the codeword.

15. The apparatus of claim 14, wherein the symbols have values selected from a set of at least three values.

16. The apparatus of claim 14, wherein the first and second input signals are cross-coupled to the frequency-dependent inverting inputs via series capacitors.

17. The apparatus of claim 14, wherein the first and second amplifier elements are MOS transistors.

18. The apparatus of claim 17, wherein the first and second input signals are received via a multi-wire bus.

19. The apparatus of claim 14, wherein the first and second amplifier elements are arranged in a differential amplifier configuration.

20. The apparatus of claim 14, wherein the amplified codeword identification signal is part of a set of amplified codeword identifications signals used to fully determine the set of output bits.