INTERFACE CIRCUIT

• US 20160077994A1
• Filed: 03/13/2015
• Published: 03/17/2016
• Est. Priority Date: 09/11/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hamada, Ken, Fujisawa, Toshio, Kondo, Nobuhiro
• Granted Patent: US 9,720,866 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard.

Claims

1. An interface circuit comprising:

a first module that executes protocol control in compliance with a first interface standard;

a second module that is provided separately from the first module and executes protocol control in compliance with a second interface standard; and

a third module that is provided for a physical layer shared between the first interface standard and the second interface standard.

2. The interface circuit according to claim 1, wherein the first interface standard is a UFS (Universal Flash Storage) standard, and the second interface standard is an M-PCIe (Mobile-Peripheral Component Interconnect Express) standard.

3. The interface circuit according to claim 1, comprising a switch control unit that switches the destination for connection of the third module to the first module or the second module.

4. The interface circuit according to claim 1, wherein the first module conforms to UniPro (Unified Protocol).

5. The interface circuit according to claim 1, wherein the second module is provided for a transaction layer and a data link layer, and wherein the third module is provided for an M-PHY (Mobile-Physical Layer).

6. The interface circuit according to claim 1, wherein the second module is provided for a transaction layer and a data link layer, and wherein the third module is provided for an M-PHY (Mobile-Physical Layer).

7. An interface circuit according to claim 1 further comprising:

a first pin that is intrinsic to the first interface standard; and

a second pin that is intrinsic to the second interface standard.

8. The interface circuit according to claim 7, wherein the first interface standard is an M-PCIe (Mobile-Peripheral Component Interconnect Express) standard, and the second interface standard is a PCIe (Peripheral Component Interconnect Express) standard.

9. The interface circuit according to claim 8, wherein the first module includes a first MAC (Media Access Layer) in conformity with an RMMI (Reference M-PHY Module Interface).

10. The interface circuit according to claim 8, wherein the second module includes a second MAC in conformity with a PIPE (Physical Interface for PCI Express).

11. The interface circuit according to claim 7, comprising a switch control unit that switches the destination for connection of the third module to the first module or the second module.

12. The interface circuit according to claim 7, wherein the second module is provided for a transaction layer and a data link layer, and wherein the third module is provided for an M-PHY (Mobile-Physical Layer).

13. An interface circuit according to claim 7 further comprising:

a first pin that is intrinsic to the first interface standard; and

a second pin that is intrinsic to the second interface standard.

14. An interface circuit comprising:

a first module that executes protocol control in compliance with a first interface standard;

a second module that is provided separately from the first module and executes protocol control shared between a second interface standard and a third interface standard;

a third module that is provided for a physical layer shared between the first interface standard and the second interface standard; and

a fourth module that is provided separately from the third module and is provided for a physical layer in compliance with the third interface standard.

15. The interface circuit according to claim 14, wherein the first interface standard is a UFS (Universal Flash Storage) standard, the second interface standard is an M-PCIe (Mobile-Peripheral Component Interconnect Express) standard, and the third interface standard is a PCIe (Peripheral Component Interconnect Express) standard.

16. The interface circuit according to claim 14, comprising:

a first switch control unit that switches the destination for connection of the third module to the first module or the second module; and

a second switch control unit that switches the destination for connection of the second module to the third module or the fourth module.

17. The interface circuit according to claim 14, wherein the first module conforms to UniPro.

18. The interface circuit according to claim 14, wherein the second module is provided for a transaction layer and a data link layer.

19. The interface circuit according to claim 14, wherein the third module is provided for an M-PHY, and wherein the fourth module is provided for a PCIe PHY.

20. An interface circuit according to claim 14 further comprising:

a first pin that is intrinsic to the first interface standard; and

a second pin that is intrinsic to the second interface standard; and

a third pin that is intrinsic to the third interface standard.