RESISTIVE MEMORY DEVICE AND CONTROL METHOD THEREOF

• US 20160078937A1
• Filed: 09/16/2014
• Published: 03/17/2016
• Est. Priority Date: 09/16/2014
• Status: Abandoned Application

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Hung, Hsi-Hsien, Shieh, Ming-Huei, Ryu, Douk Hyoun
• Application Number:
  US14/487,399
• Publication Number:
  US 20160078937A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials

Abstract

A resistive memory device is provided. A first cell is coupled to a word line, a first bit line and a source line. A second cell is coupled to the word line, a second bit line and the source line. A control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell and execute a reset operation for the second cell. After the set and the reset operations, the resistance of the first cell is less than the resistance of the second cell. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level.

Claims

1. A resistive memory device, comprising:

a first cell coupled to a word line, a first bit line and a source line;

a second cell coupled to the word line, a second bit line and the source line; and

a control circuit controlling levels of the word line, the first bit line and the source line to execute a set operation for the first cell such that the first cell has a first resistance, and controlling levels of the word line, the second bit line and the source line to execute a reset operation for the second cell such that the second cell has a second resistance greater than the first resistance,

wherein during the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level and during the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level,

wherein the pre-determined level is a ground level and the control circuit simultaneously executes the set and reset operations.

3. The resistive memory device as claimed in claim 1, wherein during the executions of the set and the reset operations, the control circuit asserts the first bit line at a setting level and asserts the second bit line at a reset level lower than the setting level.

4. The resistive memory device as claimed in claim 3, wherein the pre-determined level is between the setting level and the reset level.

6. The resistive memory device as claimed in claim 1, wherein the control circuit controls the levels of the word line, the first bit line, the second bit line and the source line to execute a verify operation to read the first and the second resistances, and during the execution of the verify operation, the level of the source line is the pre-determined level.

7. The resistive memory device as claimed in claim 1, wherein during the execution of the verify operation, the levels of the first and the second bit lines are the same.

8. The resistive memory device as claimed in claim 7, wherein the control circuit comprises a sensing amplifier unit, and during the execution of the verify operation, the sensing amplifying unit compares the first resistance with a reference resistance to identify data stored in the first cell.

9. The resistive memory device as claimed in claim 7, wherein the first cell comprises a first sub-cell and a second sub-cell, the control circuit comprises a sensing amplifying unit, and during the execution of the verify operation, the sensing amplifier unit reads resistances of the first and the second sub-cells to identify data stored in the first cell.

10. The resistive memory device as claimed in claim 1, further comprising:

a third cell coupled to the word line, a third bit line and the source line, wherein the third bit line is disposed between the first and the second bit lines, when the control circuit executes the set operation or the reset operation, the control circuit asserts a level of the third bit line at the pre-determined level, and no current path is formed in the third cell for no operation of the selected third cell.

2. (canceled)

5. (canceled)

11. A control method for a resistive memory device comprising a first cell and a second cell, wherein the first cell is coupled to a word line, a first bit line and a source line and the second cell is coupled to the word line, a second bit line and the source line, the control method comprising:

executing a set operation such that the first cell has a first resistance, wherein the set operation comprises;

providing a pre-determined level to the source line;

executing a reset operation such that the second cell has a second resistance higher than the first resistance, wherein the reset operation comprises;

providing the pre-determined level to the source line,

wherein the pre-determined level is a ground level and the set and reset operations are simultaneously executed.

13. The control method as claimed in claim 11, wherein when the set and the reset operation are executed, a setting level is provided to the first bit line and a reset level is provided to the second bit line, and the reset level is lower than the setting level.

14. The control method as claimed in claim 13, wherein the pre-determined level is between the setting level and the reset level.

16. The control method as claimed in claim 11, further comprising:

executing a verify operation to detect the first and second resistances, wherein the verify operation comprises;

providing the pre-determined level to the source line.

17. The control method as claimed in claim 16, wherein the verify operation comprises:

providing a reading level to the first and the second bit lines.

18. The control method as claimed in claim 17, wherein the verify operation comprises:

comparing the first resistance with a reference resistance.

19. The control method as claimed in claim 17, wherein the first cell comprises a first sub-cell and a second sub-cell, the verify operation is to read resistances of the first sub-cell and the second sub-cell and identifying the data stored in the first cell according to the read reset.

20. The control method as claimed in claim 11, wherein the resistive memory device further comprises a third cell coupled to the word line, a third bit line and the source line, the third bit line is disposed between the first and second bit lines, when the set operation or the reset operation is executed, and the pre-determined level is provided to the third bit line.

12. (canceled)

15. (canceled)